M25P128-VMF6G STMICROELECTRONICS [STMicroelectronics], M25P128-VMF6G Datasheet - Page 11

• Manufacturer Part Number: M25P128-VMF6G
• Description: 128 Mbit (Multilevel), Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M25P128
4.5
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See
detailed description of the Status Register bits.
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P128 features the following data protection mechanisms:
Table 2.
1.
BP2 Bit BP1 Bit BP0 Bit
Status Register Content
The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
0
0
0
0
1
1
1
1
Power On Reset and an internal timer (t
changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected
Mode (HPM).
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Protected Area Sizes
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
none
Upper 64th (1 Sector, 2Mb)
Upper 32nd (2 Sectors, 4Mb)
Upper 16nd (4 Sectors, 8Mb)
Upper 8nd (8 Sectors, 16Mb)
Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47)
Upper Half (32 Sectors, 64Mb)
All sectors (64 Sectors, 128Mb)
Protected Area
Rev. 1
Section 6.4: Read Status Register (RDSR)
PUW
) can provide protection against inadvertant
Memory Content
All Sectors (Sectors 0 to 63)
Sectors 0 to 62
Sectors 0 to 61
Sectors 0 to 59
Sectors 0 to 55
Lower Half (Sectors 0 to 31)
none
Unprotected Area
Operating features
for a
(1)
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