M25P128-VMF6G STMICROELECTRONICS [STMicroelectronics], M25P128-VMF6G Datasheet - Page 9

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M25P128-VMF6G

Manufacturer Part Number
M25P128-VMF6G
Description
128 Mbit (Multilevel), Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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M25P128
3
Figure 4.
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5.
CPOL
0
1
SPI Interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
(ST6, ST7, ST9,
ST10, Others)
CPHA
Bus Master
0
1
Bus Master and Memory Devices on the SPI Bus
SPI Modes Supported
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in Stand-by mode and not transferring data:
CS2
CPOL=0, CPHA=0
CPOL=1, CPHA=1
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
CS1
D
Q
C
C
SDO
SDI
SCK
R
MSB
(2)
S
SPI Memory
C Q D
Device
W
HOLD
V
CC
Rev. 1
R
(2)
S
SPI Memory
C Q D
Device
Figure
W
HOLD
MSB
5, is the clock polarity when the
V
CC
R
(2)
S
SPI Memory
C Q D
Device
W
AI03746e
SPI modes
HOLD
V
CC
V
AI01438B
CC
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