M25P128-VMF6G STMICROELECTRONICS [STMicroelectronics], M25P128-VMF6G Datasheet - Page 17

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M25P128-VMF6G

Manufacturer Part Number
M25P128-VMF6G
Description
128 Mbit (Multilevel), Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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M25P128
6.1
6.2
Write Enable (WREN)
The Write Enable (WREN) instruction
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 8.
Write Disable (WRDI)
The Write Disable (WRDI) instruction
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Figure 9.
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Write Enable (WREN) Instruction Sequence
Write Disable (WRDI) Instruction Sequence
S
C
D
Q
S
C
D
Q
Rev. 1
(Figure
High Impedance
High Impedance
(Figure
0
0
1
1
2
2
Instruction
Instruction
9) resets the Write Enable Latch (WEL) bit.
8) sets the Write Enable Latch (WEL) bit.
3
3
4
4
5
5
6
6
7
7
AI02281E
AI03750D
Instructions
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