M25P128-VMF6G STMICROELECTRONICS [STMicroelectronics], M25P128-VMF6G Datasheet - Page 24

• Manufacturer Part Number: M25P128-VMF6G
• Description: 128 Mbit (Multilevel), Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Instructions
6.7
24/41
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) Instruction and Data-Out
S
C
D
Q
S
C
D
Q
Sequence
0
7
32 33 34
1
6
High Impedance
2
Dummy Byte
5
Instruction
3
4
35
4
3
36 37 38 39 40 41 42 43 44 45 46
5
2
6
1
7
0
MSB
23
8
7
Rev. 1
Figure
22 21
9 10
24 BIT ADDRESS
6
DATA OUT 1
5
14.
4
C
3
28 29 30 31
3
, during the falling edge of Serial Clock (C).
2
2
1
1
0
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
0
MSB
M25P128
7
AI04006