TS2GDOM40V TRANSCEND [Transcend Information. Inc.], TS2GDOM40V Datasheet - Page 29

• Manufacturer Part Number: TS2GDOM40V
• Description: 40-Pin IDE Flash Module
• Manufacturer: TRANSCEND [Transcend Information. Inc.]

True IDE Multiword DMA Mode Read/Write Timing Specification
Notes:
Transcend Information Inc.
T
1
T
1
T
1
t
t
t
t
t
t
t
KW
t
t
t
t
t
LW
t
t
KR
LR
2
t
r
2
M
r
2
D
E
G
H
N
0
F
J
Z
r
I
(1) t
a
a
a
8
8
8
minimum command recovery time or command inactive time for input and output cycles respectively. The
actual cycle time equals the sum of the actual command active time and the actual command inactive time.
The three timing requirements of t
is greater than the sum of t
implementation can lengthen either or both of t
equal to or greater than the value reported in the device’s identify device data.
n
n
Cycle time (min)
-IORD / -IOWR asserted width(min)
-IORD data access (max)
-IORD data hold (min)
-IORD/-IOWR data setup (min)
-IOWR data hold (min)
DMACK to –IORD/-IOWR setup (min)
-IORD / -IOWR to -DMACK hold (min)
-IORD negated width (min)
-IOWR negated width (min)
-IORD to DMARQ delay (max)
-IOWR to DMARQ delay (max)
CS(1:0) valid to –IORD / -IOWR
CS(1:0) hold
-DMACK
n
M
M
M
0
s
s
s
is the minimum total cycle time and t
B
B
B
c
c
c
e
e
e
~
~
~
n
n
n
8
8
d
8
d
d
G
G
G
4
4
4
B
B
B
0
0
0
1
Item
-
-
-
P
P
P
i
i
i
n
n
n
I
I
I
D
D
D
D
1
1
and t
E
E
E
0
F
KR
F
F
, t
l
D
l
l
or t
1
a
, t
a
a
KR
s
s
s
KW
D
, and t
h
h
is the minimum command active time, while t
h
Mode 0
.for input and output cycles respectively. This means a host
(ns)
480
215
150
100
215
120
M
20
20
50
40
50
15
20
M
M
5
0
D
KW
29
o
o
o
and either of t
shall be met. The minimum total cycle time requirement
d
d
d
u
u
u
l
Mode 1
l
l
e
e
e
150
(ns)
80
60
30
15
50
50
40
40
30
10
25
5
0
5
KR
, and t
Mode 2
(ns)
120
70
50
20
10
25
25
35
35
25
10
25
5
0
5
KW
as needed to ensure that t
Mode 3
(ns)
100
65
15
25
25
35
10
10
25
50
35
5
5
0
5
KR
and t
Mode 4
KW
(ns)
80
55
45
10
20
20
35
35
10
25
5
5
0
5
5
are the
Ver 1.7
0
is