TS2GDOM40V TRANSCEND [Transcend Information. Inc.], TS2GDOM40V Datasheet - Page 41

• Manufacturer Part Number: TS2GDOM40V
• Description: 40-Pin IDE Flash Module
• Manufacturer: TRANSCEND [Transcend Information. Inc.]

Host Terminating an Ultra DMA Data-In Burst
diagram is shown in below: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters
are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:
Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra
(b) The host shall initiate Ultra DMA data burst termination by negating -HDMARDY. The host shall
(c) The device shall stop generating DSTROBE edges within t
(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two
(e) The host shall assert STOP no sooner than t
(f) The device shall negate DMARQ within t
(g) If DSTROBE is negated, the device shall assert DSTROBE within t
(h) The device shall release D[15:00] no later than t
(i) The host shall drive D[15:00] no sooner than t
(j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00]
(k) The host shall negate -DMACK no sooner than t
(l) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(m) The device shall compare the CRC data received from the host with the results of its own CRC
(n) While operating in True IDE mode, the device shall release DSTROBE within t
(o) The host shall neither negate STOP nor assert -HDMARDY until at least t
assert DMARQ again until after the Ultra DMA data burst is terminated.
STOP. No data shall be transferred during this assertion. The host shall ignore this transition on
DSTROBE. DSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
the host may first drive D[15:00] with the result of its CRC calculation (see ATA specification Ultra DMA
CRC Calculation).
during (9), the host shall place the result of its CRC calculation on D[15:00] (see ATA specification
Ultra DMA CRC Calculation).
negated DMARQ and the host has asserted STOP and negated -HDMARDY, and no sooner than t
after the host places the result of its CRC calculation on D[15:00].
calculation. If a miscompare error occurs during one or more Ultra DMA data burst for any one
command, at the end of the command, the device shall report the first error that occurred (see ATA
specification Ultra DMA CRC Calculation)
negates -DMACK.
negated -DMACK.
Transcend Information Inc.
T
1
T
1
T
1
The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
DMA data burst has been transferred.
continue to negate -HDMARDY until the Ultra DMA data burst is terminated.
additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the
host shall be prepared to receive zero, one, two or three additional data words. The additional data
words are a result of cable round trip delay and t
STOP again until after the Ultra DMA data burst is terminated.
2
r
2
r
2
r
a
a
a
8
8
8
n
n
n
M
M
M
s
s
s
B
B
B
c
c
c
e
e
e
~
~
~
n
n
n
8
8
d
8
d
d
G
G
G
4
4
4
B
B
B
0
0
0
-
-
-
P
P
P
i
i
i
n
n
n
I
I
I
D
D
D
E
E
E
F
F
F
l
l
l
a
a
a
s
LI
s
s
after the host has asserted STOP. The device shall not
h
h
h
RP
ZAH
M
M
M
after negating -HDMARDY. The host shall not negate
41
o
o
AZ
MLI
o
after the device has negated DMARQ. For this step,
RFS
d
d
d
after negating DMARQ.
after the device has asserted DSTROBE and
u
u
u
timing for the device.
l
l
l
e
e
e
RFS
of the host negating -HDMARDY
LI
after the host has asserted
ACK
after the host has
IORDYZ
after the host
Ver 1.7
DVS