TS2GDOM40V TRANSCEND [Transcend Information. Inc.], TS2GDOM40V Datasheet - Page 49

• Manufacturer Part Number: TS2GDOM40V
• Description: 40-Pin IDE Flash Module
• Manufacturer: TRANSCEND [Transcend Information. Inc.]

Host Terminating an Ultra DMA Data-Out Burst
Burst Host Termination Timing while timing parameters are specified in Page 12: Ultra DMA Data Burst
Timing Requirements and timing parameters are described in Page 13: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The host shall initiate termination of an Ultra DMA data burst by not generating HSTROBE edges.
(b) The host shall assert STOP no sooner than t
(c) The device shall negate DMARQ within t
(d) The device shall negate -DDMARDY within t
(e) If HSTROBE is negated, the host shall assert HSTROBE within t
(f) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA
(g) The host shall negate -DMACK no sooner than t
(h) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.
(i) The device shall compare the CRC data received from the host with the results of its own CRC
(j) While operating in True IDE mode, the device shall release -DDMARDY within t
(k) The host shall neither negate STOP nor negate HSTROBE until at least t
(l) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least t
shall not negate STOP again until after the Ultra DMA data burst is terminated.
DMARQ again until after the Ultra DMA data burst is terminated.
assert -DDMARDY again until after the Ultra DMA data burst termination is complete.
DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on
HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.
CRC Calculation).
and the device has negated DMARQ and -DDMARDY, and no sooner than t
of its CRC calculation on D[15:00].
calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one
command, at the end of the command, the device shall report the first error that occurred (see ATA
specification Ultra DMA CRC Calculation).
has negated -DMACK.
negating DMACK..
Transcend Information Inc.
T
1
T
1
T
1
Termination of an Ultra DMA Data-Out burst by the host is shown in below: Ultra DMA Data-Out
2
r
2
r
2
r
a
a
a
8
8
8
n
n
n
M
M
M
s
s
s
B
B
B
c
c
c
e
e
e
~
~
~
n
n
n
8
8
d
8
d
d
G
G
G
4
4
4
B
B
B
0
0
0
-
-
-
P
P
P
i
i
i
n
n
n
I
I
I
D
D
D
E
E
E
F
F
F
l
l
l
a
a
a
s
s
s
LI
h
h
h
after the host asserts STOP. The device shall not assert
LI
SS
M
M
M
after the host has negated STOP. The device shall not
after it last generated an HSTROBE edge.The host
49
MLI
o
o
o
d
d
d
after the host has asserted HSTROBE and STOP
u
u
u
l
l
l
e
e
e
LI
after the device has negated
ACK
DVS
after negating -DMACK.
after placing the result
IORDYZ
after the host
ACK
Ver 1.7
after