TS2GDOM40V TRANSCEND [Transcend Information. Inc.], TS2GDOM40V Datasheet - Page 40

• Manufacturer Part Number: TS2GDOM40V
• Description: 40-Pin IDE Flash Module
• Manufacturer: TRANSCEND [Transcend Information. Inc.]

Device Terminating an Ultra DMA Data-In Burst
diagram is shown in below: Ultra DMA Data-In Burst Device Termination Timing. The timing parameters
are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:
Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
(a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data
(b) The device shall pause an Ultra DMA data burst by not generating DSTROBE edges.
(c) NOTE − The host shall not immediately assert STOP to initiate Ultra DMA data burst termination
(d) The device shall resume an Ultra DMA data burst by generating a DSTROBE edge.
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ
burst has been transferred.
when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to
initiate Ultra DMA data burst termination, the host shall negate -HDMARDY and wait t
asserting STOP.
Transcend Information Inc.
T
1
T
1
T
1
The device terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
2
r
2
r
2
r
a
and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.
a
NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.
a
8
8
8
n
n
n
M
ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.
M
M
s
s
s
B
B
B
c
c
c
e
e
e
~
~
~
n
n
n
8
8
d
8
d
d
G
G
G
4
4
4
B
B
B
0
0
0
-
-
-
P
P
P
i
i
i
n
n
n
I
I
I
D
D
D
E
E
E
F
F
F
l
l
l
a
a
a
s
s
s
h
h
h
M
M
M
40
o
o
o
d
d
d
u
u
u
l
l
l
e
e
e
RP
before
Ver 1.7