ADF4154 Analog Devices, ADF4154 Datasheet
ADF4154
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ADF4154 Summary of contents
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... A key feature of the ADF4154 is the fast-lock mode with a built- in timer. The user can program a predetermined count-down time value so that the PLL will remain in wide bandwidth mode, instead of having to control this time externally ...
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... ADF4154 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Characteristics..................................................................... 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Pin Function Descriptions...................... 6 Typical Performance Characteristics ............................................. 7 Circuit Description........................................................................... 9 Reference Input Section............................................................... 9 RF Input Stage............................................................................... 9 RF INT Divider............................................................................. 9 INT, FRAC, MOD, and R Relationship...................................... Counter ................................................................................ 9 Phase Frequency Detector (PFD) and Charge Pump.............. 9 MUXOUT and Lock Detect ...
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... The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value). The value given is the lowest noise mode. 6 The phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the HP8562E spectrum analyzer MHz ...
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... ADF4154 TIMING CHARACTERISTICS Table SDV = 2 3 noted; dBm referred to 50 Ω. 1 Parameter Limit MIN MAX Guaranteed by design, but not production tested. CLOCK DB23 (MSB) DATA ...
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... ESD sensitive. Proper precautions should be taken for handling and assembly. −40°C to +85°C 2 GND = −65°C to +150°C DD 150°C 150.4°C/W 122°C/W 216°C/W 215°C 220°C Rev Page GND GND = DV = SDV . ADF4154 ...
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... CPmax has a value ± 10 has a value ± 10%. SDV Rev Page CPGND MUXOUT 1 15 PIN 1 INDICATOR LE AGND 14 2 ADF4154 DATA AGND 13 3 TOP VIEW CLK SDV Figure 4. LFCSP Pin Configuration to the external loop filter, which in turn drives ...
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... TYPICAL PERFORMANCE CHARACTERISTICS Figure 5 to Figure 10, and Figure 12: RF Modulus = 130, Fraction = 30/130, and I Loop Bandwidth = 20 kHz, Reference = 26 MHz, VCO = Vari-L VCO190-1750T, Evaluation Board = EVAL-ADF4154EB1. Measurements were taken on the HP8562E spectrum analyzer 3V – 5mA CP REFERENCE PFD FREQUENCY = 26MHz –20 LEVEL = – ...
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... ADF4154 –130 –140 –150 –160 –170 100 1000 10000 PHASE DETECTOR FREQUENCY (kHz) Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode –5 – 4/5 –15 –20 –25 –30 –35 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY (GHz) Figure 12. RF Input Sensitivity –1 –2 – ...
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... RF N-DIVIDER N = INT + FRAC/MOD N COUNTER THIRD ORDER FRACTIONAL INTERPOLATOR INT MOD FRAC REG REG VALUE Figure 19. A and B Counters CLR1 CHARGE U3 DELAY PUMP CLR2 DOWN Figure 20. PFD Simplified Schematic ADF4154 (2) TO PFD CP ...
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... LOGIC HIGH Figure 21. MUXOUT Schematic INPUT SHIFT REGISTERS The ADF4154 digital section includes a 4-bit RF R counter, a 9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit modulus counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. ...
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... DB6 DB5 DB4 DB3 CONTROL BITS DB2 DB1 DB0 T1 C2 (1) C1 (1) RESERVED RESERVED ADF4154 N-DIVIDER REG CONTROL BITS DB2 DB1 DB0 F1 C2 (0) C1 (0) R-DIVIDER REG CONTROL BITS DB2 DB1 DB0 M1 C2 (0) C1 (1) CONTROL REG CONTROL BITS DB2 DB1 ...
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... ADF4154 Table 8. N-Divider Register Map 9-BIT INTEGER VALUE (INT) DB23 DB22 DB21 DB20 DB19 DB18 DB17 N8 N7 FL1 FL1 FAST-LOCK 0 NORMAL OPERATION 1 FAST-LOCK ENABLED ...
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... Rev Page DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 INTERPOLATOR MODULUS VALUE (MOD) .......... .......... .......... .......... . . . . .......... . . . . .......... . . . . .......... 4092 .......... 4093 .......... 4094 .......... 4095 ADF4154 CONTROL BITS DB1 DB0 C2 (0) C1 (1) ...
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... ADF4154 Table 10. Control Register Map RESERVED DB15 DB14 DB13 ÷3 CP0 CP1 CURRENT SETTING DB12 DB11 ...
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... The on-chip control register is programmed by setting R2[ [0, 1]. Table 10 shows the input data format for programming this register. RF Counter Reset DB3 is the RF counter reset bit for the ADF4154. When this is 1, the RF synthesizer counters are held in reset. For normal operation, this bit should be 0. Rev Page ADF4154 to the PFD input ...
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... When this bit is programmed consecutive reference cycles must occur before digital lock detect is set. Phase Detector Polarity DB6 in the ADF4154 sets the phase detector polarity. When the VCO characteristics are positive, this should be set to 1. When they are negative, it should be set to 0. ...
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... SPURIOUS OPTIMIZATION AND FAST-LOCK The ADF4154 can be optimized for low spurious signals by using the noise and spur register. However, in order to achieve ) required at RES fast-lock time, a wider loop bandwidth is needed. Note that a ...
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... Various passive and active filter architectures are allowed. Rev ADIsimPLL allows analysis of the ADF4154. INTERFACING The ADF4154 has a simple, SPI® compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data VCO transfer. When LE (latch enable) is high, the 22 bits that have ...
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... The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, bring the I/O port driving LE low. Each latch of the ADF4154 needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the MicroConverter to the device. After the third byte is written, the LE input should be brought high to complete the transfer ...
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... Thin Shrink Small Outline Package (TSSOP) ADF4154BRU-REEL Thin Shrink Small Outline Package (TSSOP) ADF4154BRU-REEL7 Thin Shrink Small Outline Package (TSSOP) ADF4154BCP Lead Frame Chip Scale Package (LFCSP) ADF4154BCP-REEL Lead Frame Chip Scale Package (LFCSP) ADF4154BCP-REEL7 Lead Frame Chip Scale Package (LFCSP) EVAL-ADF4154EB1 2 Purchase of licensed I C components of Analog Devices, Inc ...