IDT72V36100 IDT [Integrated Device Technology], IDT72V36100 Datasheet - Page 33

• Manufacturer Part Number: IDT72V36100
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
WCLK
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the
2. In FWFT mode: D = maximum FIFO depth. D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680,
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
WCLK
RCLK
RCLK
WEN
WEN
REN
REN
IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
PAE
HF
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
[
D-1
n + 1 words in FIFO
t
2
CLKH
D/2 words in FIFO
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
n words in FIFO
+ 1
]
words in FIFO
t
CLKH
(1)
(2) ,
,
(2)
(3)
t
t
ENS
ENS
t
CLKL
TM
36-BIT FIFO
t
CLKL
33
t
ENH
t
t
ENH
PAEA
t
HF
t
ENS
t
ENS
[
n + 1 words in FIFO
n + 2 words in FIFO
D/2 + 1 words in FIFO
D-1
2
+ 2
]
words in FIFO
t
PAEA
t
HF
(2) ,
(3)
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
n + 1 words in FIFO
[
D-1
TEMPERATURE RANGES
n words in FIFO
2
D/2 words in FIFO
+ 1
]
words in FIFO
4667 drw 27
4667 drw 26
(2) ,
(1)
,
(3)
(2)