IDT72V36102 IDT [Integrated Device Technology], IDT72V36102 Datasheet - Page 7

• Manufacturer Part Number: IDT72V36102
• Description: 3.3 VOLT CMOS SyncBiFIFO-TM
• Manufacturer: IDT [Integrated Device Technology]

DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
CLKA and CLKB set to f
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
100
The I
With I
50
80
70
60
40
30
20
90
10
0
P
where:
N
C
f
CC(f)
o
0
CC(f)
T
L
= V
current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3682/72V3692/72V36102 with
taken from Figure 1, the maximum power dissipation (P
CC
=
=
=
x I
10
CC
S
. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
f
T
C
(f) + Σ(C
data
A
L
= 25°C
= 0 pF
= 1/2 f
N
number of outputs = 36
output capacitance load
switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (I
L
S
x V
20
CC
2
X fo)
30
V
f
S
CC =
40

TM
Clock Frequency
3.3V
T
) of these FIFOs may be calculated by:
7
50

MHz
CC
60
) vs. Clock Frequency (f
70
COMMERCIAL TEMPERATURE RANGE
V
CC =
S
3.6V
)
80
V
CC =
3.0V
90
4679 drw 04
100