lxt9781 Intel Corporation, lxt9781 Datasheet - Page 14

• Manufacturer Part Number: lxt9781
• Description: Fast Ethernet 10/100 Multi-port Transceiver With Rmii
• Manufacturer: Intel Corporation

LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII
14
1. Type Column Coding: I = Input, O = Output, OD = Open Drain
2. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
3. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761.
9761 Pin#
where X is the register number (0-32) and Y is the bit number (0-15).
Table 1.
PQFP
42
41
19
18
10
63
56
43
20
11
64
57
44
21
12
9
3
2
–
–
–
–
4
–
–
5
–
–
LXT97x1 RMII Signal Descriptions (Continued)
PQFP
42
41
35
34
26
25
19
18
10
63
56
43
36
27
20
64
57
44
37
28
21
12
11
9
3
2
4
5
9781 Pin#
PBGA
W6
R2
R1
N2
N1
H3
H1
C2
C1
R3
N3
H4
R4
N4
D1
K3
K2
E3
E1
V6
Y3
K4
F1
B3
V3
F2
L1
J1
RXD2_0
RXD2_1
RXD3_0
RXD3_1
RXD4_0
RXD4_1
RXD5_0
RXD5_1
RXD6_0
RXD6_1
RXD7_0
RXD7_1
CRS_DV0
CRS_DV1
CRS_DV2
CRS_DV3
CRS_DV4
CRS_DV5
CRS_DV6
CRS_DV7
RXER0
RXER1
RXER2
RXER3
RXER4
RXER5
RXER6
RXER7
Symbol
Type
O
O
O
O
O
O
O
O
1
Receive Data - Port 2. Receive data signals (2-bit parallel di-
bits) are driven synchronously to REFCLK.
Receive Data - Port 3. Receive data signals (2-bit parallel di-
bits) are driven synchronously to REFCLK.
Receive Data - Port 4. Receive data signals (2-bit parallel di-
bits) are driven synchronously to REFCLK.
Receive Data - Port 5. Receive data signals (2-bit parallel
di-bits) are driven synchronously to REFCLK.
Receive Data - Port 6. Receive data signals (2-bit parallel di-
bits) are driven synchronously to REFCLK.
Receive Data - Port 7. Receive data signals (2-bit parallel
di-bits) are driven synchronously to REFCLK.
Carrier Sense/Receive Data Valid - Ports 0 - 7. On
detection of valid carrier, these signals are asserted
asynchronously with respect to REFCLK. CRS_DVn is
deasserted on loss of carrier, synchronous to REFCLK.
Receive Error - Ports 0 - 7. These signals are synchronous
to the respective REFCLK. Active High indicates that
received code group is invalid, or that PLL is not locked.
Signal Description
2, 3
Datasheet