lxt9781 Intel Corporation, lxt9781 Datasheet - Page 42

• Manufacturer Part Number: lxt9781
• Description: Fast Ethernet 10/100 Multi-port Transceiver With Rmii
• Manufacturer: Intel Corporation

LXT9761/9781 — Fast Ethernet 10/100 Multi-Port Transceiver with RMII
2.9.5
2.10
2.10.1
2.10.2
42
REFCLK
1. When network activity is detected, the LXT97x1 asserts CRS_DV asynchronously with respect to REFCLK.
2. After CRS_DV is asserted, the LXT97x1 will zero-stuff the RXData bits until the received data has been processed through the
3. When network activity ceases, the LXT97x1 de-asserts CRS_DV synchronously with respect to REFCLK. CRS_DV will toggle
CRS_DV
RXD(1)
RXD(0)
FIFO.
until all data in the FIFO has been processed through the RMII. Once the FIFO is empty, the LXT97x1 will drive the status bits
selected by the Out-of-Band Signalling Register (refer to
Figure 20. RMII Programmable Out of Band Signalling
status 1
status 0
Out-of-Band Signalling
The LXT97x1 provides an out-of-band signalling option to transfer status information across the
RMII receive interface. Enabled when 25.0=1, this feature uses the RXD(1:0) data bus during the
IPG time as shown in
The two status bits that are transferred across the RXD bus are software selectable via Register 25
(refer to
In normal operation the LXT97x1 stuffs the RXD bus with zeros during the Inter-Packet Gap
(IPG). A software-selectable bit enables the RMII out of band signalling feature. Once this bit is
set the LXT97x1 replaces those zeros with the selected status bits during the IPG.
Boundary Scan (JTAG1149.1) Functions
The LXT97x1 includes a IEEE 1149.1 boundary scan test port for board level testing. All digital
input, output, and input/output pins are accessible.
Boundary Scan Interface
This interface consists of five pins (TMS,TDI,TDO, TCK and TRST). It includes a state machine,
data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is
internally pulled down. TDO does not have an internal pull-up or pull-down.
State Machine
The TAP controller is a 16 Bit state machine driven by the TCK and TMS pins. Upon reset the
TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS is high for five
TCK periods.
status 1
status 0
Table 49 on page
0s
0s
data
data
Figure
75).
20.
data
data
Table 49 on page
data
data
data
data
75) on the RXD outputs.
status 1
status 0
status 1
status 0
status 1
status 0
status 1
status 0
Datasheet
status 1
status 0