lxt9781 Intel Corporation, lxt9781 Datasheet - Page 37

• Manufacturer Part Number: lxt9781
• Description: Fast Ethernet 10/100 Multi-port Transceiver With Rmii
• Manufacturer: Intel Corporation

2.7.2.4
2.8
2.8.1
Datasheet
Fiber PMD Sublayer
The LXT97x1 provides a PECL interface for connection to an external fiber-optic transceiver.
(The external transceiver provides the PMD function for fiber media.) The LXT97x1 uses an
NRZI format and operates at 100 Mbps. The LXT97x1 does not support 10FL applications.
Signal Fault Indications
The LXT97x1 Signal Detect pins receive signal fault indications from local fiber transceivers via
the SD pins. The device can also detect far end fault code in the received data stream. The
LXT97x1 “ORs” both fault conditions to set bit 1.4. Bit 1.4 is set once and clears when read.
Either fault condition causes the LXT97x1 to drop the link unless Forced Link Pass is selected
(16.14 = 1). Link down condition is then reported via interrupts and status bits.
In response to locally detected signal faults (SD activated by the local fiber transceiver), the
affected port can transmit the far end fault code if fault code transmission is enabled by bit 16.2.
10 Mbps Operation
The LXT97x1 will operate as a standard 10BASE-T transceiver and supports all the standard 10
Mbps functions.
During 10BASE-T (10T) operation, the LXT97x1 transmits and receives Manchester-encoded data
across the network link. When the MAC is not actively transmitting data, the LXT97x1 sends out
link pulses on the line.
In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals
received from the network are decoded by the LXT97x1 and sent across the RMII to the MAC.
The 10M reversed polarity correction function is the same as the 100M function described on
page
The LXT97x1 does not support fiber connections at 10 Mbps.
Preamble Handling
The LXT97x1 offers two options for preamble handling, selected by bit 16.5. In 10T Mode when
16.5 = 0, the LXT97x1 strips the entire preamble off of received packets. CRS_DV is asserted
coincident with SFD. CRS_DV is held Low for the duration of the preamble. When CRS_DV is
asserted, the very first two nibbles driven by the LXT97x1 are the SFD “5D” hex followed by the
body of the packet.
In 10T mode with 16.5 = 1, the LXT97x1 passes the preamble through the RMII and asserts
CRS_DV simultaneously.
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When bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT97x1 transmits
far end fault code if fault conditions are detected by the Signal Detect pins.
When bit 16.2 = 0, the LXT97x1 does not transmit far end fault code. It continues to transmit
idle code and may or may not drop link depending on the setting for bit 16.14.
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Fast Ethernet 10/100 Multi-Port Transceiver with RMII — LXT9761/9781
37