lxt971a Intel Corporation, lxt971a Datasheet
lxt971a
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lxt971a Summary of contents
Page 1
... This document also supports the LXT971 device. The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition can be set using auto-negotiation, parallel detection, or manual control. The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V power supply. Applications ...
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... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT971A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Base Page Exchange .............................................................................31 3.5.1.2 Next Page Exchange .............................................................................31 3.5.1.3 Controlling Auto-Negotiation...............................................................31 3.5.2 Parallel Detection ................................................................................................31 3.6 MII Operation....................................................................................................................32 3.6.1 MII Clocks ..........................................................................................................32 3.6.2 Transmit Enable ..................................................................................................33 3.6.3 Receive Data Valid .............................................................................................33 3.6.4 Carrier Sense .......................................................................................................33 3.6.5 Error Signals .......................................................................................................33 3.6.6 Collision ..............................................................................................................33 3.6.7 Loopback.............................................................................................................34 3.6.7.1 Operational Loopback ..........................................................................35 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 3 ...
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... LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.6.7.2 Test Loopback...................................................................................... 35 3.7 100 Mbps Operation ......................................................................................................... 36 3.7.1 100BASE-X Network Operations...................................................................... 36 3.7.2 Collision Indication ............................................................................................ 38 3.7.3 100BASE-X Protocol Sublayer Operations ....................................................... 38 3.7.3.1 PCS Sublayer ....................................................................................... 38 3.7.3.2 PMA Sublayer...................................................................................... 41 3.7.3.3 Twisted-Pair PMD Sublayer ................................................................ 42 3.7.3.4 Fiber PMD Sublayer ............................................................................ 43 3.8 10 Mbps Operation ........................................................................................................... 43 3.8.1 10BASE-T Preamble Handling.......................................................................... 43 3.8.2 10BASE-T Carrier Sense ................................................................................... 43 3.8.3 10BASE-T Dribble Bits ..................................................................................... 43 3 ...
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... MDIO Output Timing........................................................................................................61 38 Power-Up Timing..............................................................................................................62 39 RESET Pulse Width and Recovery Timing ......................................................................62 40 PHY Identifier Bit Mapping..............................................................................................68 41 PBGA Package Specification ............................................................................................79 42 LXT971A LQFP Package Specifications..........................................................................80 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 5 ...
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... LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Tables 1 LQFP Numeric Pin List .................................................................................................... 12 2 LXT971A MII Signal Descriptions .................................................................................. 14 3 LXT971A Network Interface Signal Descriptions ........................................................... 15 4 LXT971A Miscellaneous Signal Descriptions ................................................................. 16 5 LXT971A Power Supply Signal Descriptions.................................................................. 17 6 LXT971A JTAG Test Signal Descriptions ...................................................................... 17 7 LXT971A LED Signal Descriptions ................................................................................ 17 8 Hardware Configuration Settings ...
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... Status Register #2 (Address 17) ........................................................................................74 51 Interrupt Enable Register (Address 18).............................................................................75 52 Interrupt Status Register (Address 19, Hex 13).................................................................76 53 LED Configuration Register (Address 20, Hex 14) ..........................................................77 54 Transmit Control Register (Address 30) ...........................................................................78 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 7 ...
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... Modified text under 47 Modified Table 13 “Supported JTAG 47 Modified Table 14 “Device ID 52 Added a new 53 Replaced Figure 25 “Typical LXT971A-to-3.3 V Fiber Transceiver Interface 54 Added Figure 26 “Typical LXT971A-to-5 V Fiber Transceiver Interface 55 Added Figure 27 “ON Semiconductor Triple PECL-to-LVPECL 56 Modified Table 17 “Absolute Maximum 56 Modified Table 18 “Operating ...
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... Clock Requirements: Modified language under Clock Requirements heading. N/A Table 21 I/O Characteristics REFCLK: Changed values for Input Clock Duty Cycle under Min from and under Max from 60 to 65. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Revision 001 Revision Date: January 2001 Description 9 ...
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... LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 10 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 ...
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... TX_ER TX_CLK LED/CFG<3:1> Collision COL Detect RX_CLK RXD<3:0> RXDV CRS RX_ER Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Mode Select Register Set Logic Clock Generator Manchester 10 OSP Encoder ™ Pulse Parallel/Serial Scrambler 100 Shaper Converter & ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 1.0 Pin Assignments Figure 2. LXT971A 64-Ball PBGA Assignments 1 A MDINT REF B CLK/ SLEW0 E ADDR0 F ADDR3 G ADDR4 H RBIAS CRS TXD3 TXD0 RX_ER COL TXD2 TX_EN TX_ER TX_ RESET GND TXD1 CLK Tx MDDIS GND ...
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... Figure 3. LXT971A 64-Pin LQFP Assignments REFCLK/XI XO MDDIS RESET TXSLEW0 TXSLEW1 GND VCCIO N/C N/C GND ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 1. LQFP Numeric Pin List Pin Symbol 1 REFCLK/ MDDIS 4 RESET 5 TxSLEW0 6 TxSLEW1 7 GND 8 VCCIO 9 N/C 10 N/C 11 GND 12 ADDR0 13 ADDR1 14 ADDR2 15 ADDR3 16 ADDR4 17 RBIAS 18 GND 19 TPFOP 20 TPFON 21 VCCA 22 VCCA 23 TPFIP 24 TPFIN 25 GND 26 SD/TP 27 TDI 28 TDO 29 TMS 30 TCK ...
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... TXD3 61 GND 62 COL 63 CRS 64 MDINT Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Reference for Type Full Description I/O Table 7 on page 19 I/O Table 7 on page 19 Input Table 4 on page 18 – Table 5 on page 19 – Table 5 on page 19 ...
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... Receive Data. RXD is a bundle of parallel signals that transition O synchronously with respect to the RX_CLK. RXD<0> is the least significant bit. Receive Data Valid. The LXT971A asserts this signal when it drives O valid data on RXD. This output is synchronous to RX_CLK. Receive Error. Signals a receive error condition has occurred. ...
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... For standard digital loopback testing (Register bit 0.14 mode, the SD pin should be tied to an LVPECL logic High (2.4 V). Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 1 Type Signal Description MII Control Interface Pins Management Disable. When MDDIS is High, the MDIO is disabled from read and write operations ...
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... Sleep. When set High, this pin enables the LXT971A to go SLEEP I into a low-power sleep mode. The value of this pin can be overridden by Register bit 16.6 when in managed mode. Power Down. When set High, this pin puts the LXT971A in a PWRDWN I power-down mode. Crystal Input and Output MHz crystal oscillator circuit ...
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... Type Column Coding Input Output Analog Open Drain. 2. Pull-up/pull-down resistors can be implemented if LEDs are used in the design. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Symbol Type VCCD – Digital Power. Requires a 3.3V power supply. ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 8. LXT971A Pin Types and Modes Modes RXD 0-3 HWReset DL SFTPWRDN DL HWPWRDN High ISOLATE IPLD SLEEP High Z (High impedance) or three-state determines when the device is drawing a current of less than 20 nA. A High Z with PLD (High impedance with pull-down) state determines when the device is drawing a current of less than 20 PA ...
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... Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. The LXT971A reads its configuration pins on power-up to check for forced operation settings. If not configured for forced operation, the device uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT971A auto-negotiates with it using Fast Link Pulse (FLP) Bursts ...
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... Only a transformer, RJ-45 connector, load resistor, and bypass capacitors are required to complete this interface. On the transmit side, the LXT971A has an active internal termination and does not require external termination resistors. Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to page 18) allow the designer to match the output waveform to the magnetic characteristics ...
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... Increased MII Drive Strength A higher Media Independent Interface (MII) drive strength may be desired in some designs to drive signals over longer PCB trace lengths, or over high-capacitive loads, through multiple vias, or through a connector. The MII drive strength in the LXT971A can be increased by setting Register Datasheet Document #: 249414 Revision #: 002 Rev ...
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... The LXT971A supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT971A. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers ...
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... Link status change 3.2.3.2 Hardware Control Interface The LXT971A provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the three LED driver pins to set device configuration. Refer to the Hardware Configuration Settings section on page 30 for additional Figure 6 ...
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... MHz. Refer to 3.4 Initialization When the LXT971A is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as ...
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... Hardware Control Mode In the Hardware Control Mode, LXT971A disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT971A reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control: • ...
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... Writes Enabled) Reset MDIO Registers to values read at H/W Control Interface at last 3.4.3 Reduced Power Modes The LXT971A offers two power-down modes and a sleep mode. 3.4.3.1 Hardware Power Down The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High, the following conditions are true: • ...
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... The MDIO registers remain accessible. 3.4.3.3 Sleep Mode The LXT971A supports a power-saving sleep mode. Sleep mode is enabled when SLEEP is asserted via pin 32(LQFP)/H7(PBGA). The value of pin 32/H7 can be overridden by Register bit 16.6 when in managed mode as shown in mode when SLEEP is enabled and no energy is detected on the twisted-pair input for 1-3 seconds (the time is controlled by Register bits 16 ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.4.5 Hardware Configuration Settings The LXT971A provides a hardware option to set the initial device configuration. The hardware option uses the three LED driver pins. This provides three control bits, as listed in LED drivers can operate as either open-drain or open-source circuits as shown in Figure 8 ...
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... Each FLP burst exchanges 16 bits of data, which are referred “link code word”. All devices that support auto-negotiation must implement the “Base Page” defined by IEEE 802.3 (registers 4 and 5). LXT971A also supports the optional “Next Page” function as described in 3 ...
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... Separate channels are provided for transmitting data from the MAC to the LXT971A (TXD), and for passing data received from the line (RXD) to the MAC. Each channel has its own clock, data bus, and control signals. Nine signals are used to pass received data to the MAC: RXD< ...
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... Carrier sense is not generated when a packet is transmitted and in full-duplex mode. 3.6.5 Error Signals When LXT971A is in 100 Mbps mode and receives an invalid symbol from the network, it asserts RX_ER and drives “1110” on the RXD pins. When the MAC asserts TX_ER, the LXT971A drives “H” symbols out on the TPFOP/N pins. ...
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... LXT971A) XI Figure 12. Link Down Clock Transition RX_CLK TX_CLK 3.6.7 Loopback The LXT971A provides two loopback functions, operational and test (see paths are shown in Figure 34 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle 2.5 MHz during auto-negotiation and 10BASE-T Data & Idle Constant 25 MHz 2 ...
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... Operational loopback is not provided for 100 Mbps links, full-duplex links, or when 16 3.6.7.2 Test Loopback A test loopback function is provided for diagnostic testing of the LXT971A. During test loopback, twisted-pair and fiber interfaces are disabled. Data transmitted by the MAC is internally looped back by the LXT971A and returned to the MAC. ...
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... During 100BASE-X operation, the LXT971A transmits and receives 5-bit symbols across the network link. Figure 14 actively transmitting data, the LXT971A sends out Idle symbols on the line. In 100BASE-TX mode, the LXT971A scrambles and transmits the data to the network using MLT- 3 line code (Figure 15 on page decoded, and sent across the MII to the MAC. ...
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... S4 As shown in Figure 14 on page soon as the LXT971A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD, symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the SFD, packet data, and CRC. ...
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... COL 3.7.3 100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT971A is a Physical Layer 1 (PHY) device. The LXT971A implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u standard. The following paragraphs discuss LXT971A operation from the reference model point of view ...
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... SSD. 3.7.3.1.2 Dribble Bits The LXT971A handles dribbles bits in all modes. If one to four dribble bits are received, the nibble is passed across the MII, and padded with ones if necessary. If five to seven dribble bits are received, the second nibble is not sent to the MII bus. ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 11. 4B/5B Coding 4B Code Code Type DATA ...
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... Furthermore, 100 Mbps idle patterns will not bring Mbps link. The LXT971A reports link failure via the MII status bits (Register bits 1.2 and 17.10) and interrupt functions. Link failure causes the LXT971A to re-negotiate if auto-negotiation is enabled. ...
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... CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half- duplex mode. 3.7.3.2.4 Receive Data Valid The LXT971A asserts RX_DV to indicate that the received data maps to valid symbols. However, RXD outputs zeros until the received data is decoded and available for transfer to the controller. 3.7.3.3 ...
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... Fiber PMD Sublayer The LXT971A provides a Low Voltage PECL interface for connection to an external 3 5.0 V fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The LXT971A uses an NRZI format for the fiber interface. The fiber interface operates at 100 Mbps and does not support 10FL applications ...
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... Configuration Register, the LXT971A transmits packets, regardless of link status. 3.8.5 10BASE-T SQE (Heartbeat) By default, the Signal Quality Error (SQE) or heartbeat function is disabled on the LXT971A. To enable this function, set Register bit 16 When this function is enabled, the LXT971A asserts its COL output for 5-15 BT after each packet. See parameters. 3.8.6 ...
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... Register bits 6.1 and 6.5 are cleared when read. 3.9.2 LED Functions The LXT971A incorporates three direct LED drivers. On power up all the drivers are asserted for approximately 1 second after reset de-asserts. Each LED driver can be programmed using the LED Configuration Register (refer to • ...
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... Note: The direct drive LED outputs in this diagram are shown as active Low. 3.10 Boundary Scan (JTAG1149.1) Functions LXT971A includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. The BSDL file is available by contacting your local sales office or by accessing the Intel website (www.intel.com). ...
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... The JEDEC 8-bit identifier. The MSB is for parity and is ignored. Intel’s JEDEC (1111 1110), which becomes 111 1110. 2. See the LXT971A/972A Specification Update (document number 249354) for the current version of the Jedec continuation characters. Datasheet Document #: 249414 Revision #: 002 Rev ...
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... Application Information 4.1 Magnetics Information The LXT971A requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated protect the circuitry from static voltages across the connectors and cables. Refer to A cross-reference list of magnetic manufacturers and part numbers is available in Magnetic Manufacturers for Networking Product Applications (document number 248991) and is found on the Intel web site (www ...
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... Magnetics without a receive pair center-tap do not require termination. 4. RJ-45 connections shown are for a standard switch application. For a standard NIC RJ-45 setup, see Figure 23 on page Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 270 pF 5% TPFIP 50: 1:1 0. 50: ...
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... V current source. A separate ferrite bead (rated at 50 mA) should be used to supply center-tap current. 2. The 100 : transmit load termination resistor typically required is integrated in the LXT971A. 3. Magnetics without a receive pair center-tap do not require termination. 4. RJ-45 connections shown for standard NIC. TX/RX crossover may be required for repeater and switch applications ...
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... Figure 24. Typical MII Interface MAC Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver TX_EN TX_ER TXD<3:0> TX_CLK RX_CLK RX_DV LXT971A RX_ER RXD<3:0> CRS COL X F RJ- ...
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... The signal detect pin fiber transceiver interface should use the logic translator circuitry as shown in Figure 27. Refer to the fiber transceiver manufacturer’s recommendations for termination circuitry. Figure 26 shows a typical example of an LXT971A-to-5 V fiber transceiver interface, while Figure 27 shows the interface circuitry for the logic translator. 52 Figure ...
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... Figure 25. Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry TPFON TPFOP LXT971A SD/TP TPFIN TPFIP 1. Refer to the transceiver manufacturer’s recommendations for termination circuitry. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver +3.3V +3.3V : PFP F : : +3.3V : : +3.3V PF : : P F : : Fiber Txcvr ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 26. Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry TPFON TPFOP LXT971A SD/TP TPFIN TPFIP 1. Refer to the transceiver manufacturer’s recommendations for termination circuitry. 2. See Figure 27 54 +3.3V +3.3V PF : PF k: k: : : PF PF Semiconductor MC100LVEL92 PECL-to-LVPECL Logic Translator +3.3V PF : : ...
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... Figure 27. ON Semiconductor Triple PECL-to-LVPECL Translator 0. 82: PECL Input Signal 130: (5V Fiber Txcvr) Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 5V ON Semiconductor Vcc Vcc VBB PECL 4 17 ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 5.0 Test Specifications Note: Table 17 through Table 40 specifications of the LXT971A. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in recommended operating conditions specified in 5.1 Electrical Parameters Table 17. Absolute Maximum Ratings Parameter ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 2 1 Symbol Min Typ Max V – ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 22. I/O Characteristics - LED/CFG Pins Parameter Input Low Voltage Input High Voltage Input Current Output Low Voltage Output High Voltage Table 23. I/O Characteristics – SD/TP Pin Parameter Fiber Mode (Register bit 16 Twisted-Pair Mode (Register bit 16 100BASE-FX Mode Normal Operation – SD Input from Fiber Transceiver ...
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... Link Transmit Period Link Pulse Width 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 1 Symbol Min Typ Max Transmitter V 0.6 – ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 28. LXT971A Thermal Characteristics Parameter Package Theta-JA Theta-JC Psi - JT 60 LXT971ALC LXT971ALE x1 LQFP 1.4 64 LQFP 58 C/W 56 C/W 27 C/W 25 C/W 3.4 C/W 3.0 C/W LXT971ABE .96 64 BGA-CSP 42 C/W 20 C/W – Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 0ns Sym Min ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 29. 100BASE-TX Transmit Timing - 4B Mode TXCLK TX_EN TXD<3:0> TPFO CRS Table 30. 100BASE-TX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 100BASE-T bit time = 10 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 0ns Sym Min ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 31. 100BASE-FX Transmit Timing TXCLK TX_EN TXD<3:0> TPFO CRS Table 32. 100BASE-FX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted ...
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... Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing the duration of one bit as transferred to and from the MAC and is the reciprocal of the bit rate. 10BASE-T bit time = 10 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 33. 10BASE-T Transmit Timing TX_CLK TXD, TX_EN, TX_ER CRS TPFO Table 34. 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS de-asserted ...
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... COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Symbol Min Typ Max ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 36. Auto-Negotiation and Fast Link Pulse Timing TPFOP Figure 37. Fast Link Pulse Timing TPFOP Table 37. Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width ...
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... PHY MDC period 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Symbol Min Typ ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 40. Power-Up Timing VCC MDIO,etc Table 39. Power-Up Timing Parameters Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. 2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance - the PHY comes out of reset after a delay of No MORE Than 300 P s ...
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... Register Definitions The LXT971A register set includes multiple 16-bit registers. listing. Table complete memory map of all registers and individual register definitions. Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical Layer Link Signaling for 10/100 Mbps Auto- Negotiation” ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 72 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 ...
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... Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 73 ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 43. Control Register (Address 0) Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed Selection Auto-Negotiation 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart 0.9 Auto-Negotiation 0.8 Duplex Mode 0.7 Collision Test 0.6 Speed Selection 0.5:0 Reserved 1. R/W = Read/Write RO = Read Only SC = Self Clearing 2. Default value of Register bits 0.12, 0.13 and 0.8 are determined by the LED/CFG n pins (refer to page 30) ...
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... LL = Latching Low LH = Latching High Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Description 1 = PHY able to perform 100BASE- PHY not able to perform 100BASE- PHY able to perform full-duplex 100BASE PHY not able to perform full-duplex 100BASE PHY able to perform half-duplex 100BASE-X ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 45. PHY Identification Register 1 (Address 2) Bit Name 2.15:0 PHY ID Number Read Only Table 46. PHY Identification Register 2 (Address 3) Bit Name 3.15:10 PHY ID number Manufacturer’s 3.9:4 model number Manufacturer’s 3.3:0 revision number Read Only Figure 42. PHY Identifier Bit Mapping ...
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... Pause operation enabled for full-duplex links Pause operation disabled 100BASE-T4 capability is available 100BASE-T4 capability is not available. (The LXT971A does not support 100BASE-T4 but allows this bit to be set to advertise in the auto- negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired ...
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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 48. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved Asymmetric 5.11 Pause 5.10 Pause 5.9 100BASE-T4 100BASE-TX 5.8 full-duplex 5.7 100BASE-TX 10BASE-T 5.6 full-duplex 5.5 10BASE-T Selector Field 5.4:0 S<4:0> Read Only 78 Description 1 = Link Partner has ability to send multiple pages. ...
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... Code Field Read Only. R/W = Read/Write Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Description Ignore on read. This bit indicates the status of the auto-negotiation variable base page. It flags synchronization with the auto-negotiation state diagram, allowing detection of interrupted links ...
Page 80
... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 51. Auto-Negotiation Link Partner Next Page Receive Register (Address 8) Bit Name Next Page 8.15 (NP) Acknowledge 8.14 (ACK) Message Page 8.13 (MP) Acknowledge 2 8.12 (ACK2) Toggle 8.11 (T) Message/Unformatted 8.10:0 Code Field Read Only. 80 Description 1 = Link Partner has additional next pages to send 0 = Link Partner has no additional next pages to ...
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... The default value of Register bit 16.6 is determined by the state of the SLEEP pin 32/H7. 3. The default value of Register bit 16.0 is determined by pin 26/G2 (SD/TP). Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Description Write as zero, ignore on read Force Link pass 0 = Normal operation 1 = Disable Twisted Pair transmitter ...
Page 82
... Description Always LXT971A is operating in 100BASE-TX mode LXT971A is not operating 100BASE-TX mode LXT971A is transmitting a packet LXT971A is not transmitting a packet LXT971A is receiving a packet LXT971A is not receiving a packet Collision is occurring collision Link is up Link is down Full-duplex Half-duplex LXT971A is in auto-negotiation mode LXT971A is in manual mode. ...
Page 83
... TINT 1. R/W = Read /Write Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Description Write as 0; ignore on read. Write as 0; ignore on read. Mask for Auto Negotiate Complete 1 = Enable event to cause interrupt not allow event to cause interrupt. ...
Page 84
... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 55. Interrupt Status Register (Address 19, Hex 13) Bit Name 19.15:9 Reserved 19.8 Reserved 19.7 ANDONE 19.6 SPEEDCHG 19.5 DUPLEXCHG 19.4 LINKCHG 19.3 Reserved 19.2 MDINT 19.1 Reserved 19.0 Reserved 1. R/W = Read/Write Read Only Self Clearing. 84 Description Ignore Ignore Auto-negotiation Status 1= Auto-negotiation has completed. 0= Auto-negotiation has not completed. Speed Change Status Speed Change has occurred since last reading this register ...
Page 85
... Values are relative approximations. Not guaranteed or production tested. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Description 0000 = Display Speed Status (Continuous, Default) 0001 = Display Transmit Status (Stretched) 0010 = Display Receive Status (Stretched) 0011 = Display Collision Status (Stretched) ...
Page 86
... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 56. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name LED3 20.7:4 Programming bits 5 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. ...
Page 87
... Values are relative approximations. Not guaranteed or production tested. 2. R/W = Read/Write Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Description Ignore 1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission Normal transmission 3.0 ns (default = TXSLEW<1:0> pins ...
Page 88
... Package Specifications Figure 43. PBGA Package Specification 64-Ball Plastic Ball Grid Array Package • Part Number - LXT971ABC Commercial Temperature Range (0ºC to +70ºC) • Part Number - LXT971ABE Extended Temperature Range (-40ºC to +85ºC) 0.20 (4X) 7.00 ± 0.20 2.00 REF. OPTION: PIN A1 IDENTIFIER 1.00 ± 0.10 INK OR LASER MARKING 1.26 ± ...
Page 89
... Figure 44. LXT971A LQFP Package Specifications 64-Pin Low Profile Quad Flat Pack • Part Number - LXT971ALC Commercial Temperature Range (0ºC to +70ºC) • Part Number - LXT971ALE Extended Temperature Range (-40ºC to +85ºC) Millimeters Dim Min Max A – 1.60 A 0.05 0. 1.35 1. 0.17 0.27 D 11.85 12.15 D 9.9 10 11.85 12.15 E 9.9 10.1 1 ...
Page 90
... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 8.0 Product Ordering Information Table 59. Product Information Number DJLXT971ALC.A4 DJLXT971ALE.A4 FLLXT971ABC.A4 FLLXT971ABE.A4 Figure 45. Ordering Information - Sample DJ LXT 971A 90 Revision Qualification E001 Build Format E000 E001 Qualification Q S Product Revision xn Temperature Range ...