lxt971a Intel Corporation, lxt971a Datasheet - Page 28
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lxt971a
Manufacturer Part Number
lxt971a
Description
3.3v Dual-speed Fast Ethernet Phy Transceiver
Manufacturer
Intel Corporation
Datasheet
1.LXT971A.pdf
(90 pages)
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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
3.4.3
3.4.3.1
28
Figure 7. Initialization Sequence
Reduced Power Modes
The LXT971A offers two power-down modes and a sleep mode.
Hardware Power Down
The hardware power-down mode is controlled by the PWRDWN pin. When PWRDWN is High,
the following conditions are true:
•
•
•
•
The LXT971A network port and clock are shut down.
All outputs are three-stated.
All weak pad pull-up and pull-down resistors are disabled.
The MDIO registers are not accessible.
MDIO Controlled Operation
Reset MDIO Registers to
(MDIO Writes Enabled)
Control Interface at last
MDIO Control
values read at H/W
Hardware Reset
Mode
Software
Reset?
Yes
Low
Initialize MDIO Registers
Power-up or Reset
Read H/W Control
No
MDDIS Voltage
Interface
Level?
Disable MDIO Read and
High
Hardware Control
Write Operations
Mode
Rev. Date: August 7, 2002
Document #: 249414
Revision #: 002
Datasheet