alc203-lf Realtek Semiconductor Corporation, alc203-lf Datasheet - Page 21

• Manufacturer Part Number: alc203-lf
• Description: Two-channel Ac?97 2.3 Audio Codec
• Manufacturer: Realtek Semiconductor Corporation

6.1.20 MX2A Extended Audio Status and Control,
Default: 0000h
This register contains two active bits for power-down and status of the surrounding DACs. Bits 0, 1, and 2 are read/write bits
which are used to enable or disable VRA, DRA, and SPDIF respectively. Bits 4 and 5 are read/write bits used to determine the
AC-LINK slot assignment of the S/PDIF. Bit 10 is a read-only bit which tells the controller if the S/PDIF configuration is valid.
Two-Channel AC’97 2.3 Audio Codec
14:11
Bit
9:6
5:4
15
10
3
2
1
0
SPCV is a read-only bit that indicates whether the current S/PDIF-Out configuration is supported or not. If the
sampling rate defined in MX2C and MX32. VRA also controls the write operation of MX2Cand MX32.
frame. In this mode, MX2C is fixed at BB80h, MX32 and ADC is still controlled by VRA.
configuration is supported, SPCV is set as 1 by H/W. So driver can check this bit to determine the status of the
S/PDIF transmitter system. SPCV is always operating, independent of the SPDIF enable bit (MX2A.2). The
S/PDIF output is active if MX2A.2 is set in spite of SPCV. Once S/PDIF output is enabled but SPCV is invalid
(SPCV=0), channel status is still output, but the output data bits will be all zero.
If DRA = 1, DAC operates at a fixed 96KHz sampling rate. The PCM(n) and PCM(n+1) data is captured in the same
If VRA = 0, the ALC203’s ADC/DAC operate at a fixed 48KHz sampling rate. Otherwise, they operate at a variable
DRA can be written when (ID=00)&(DSA=00), otherwise it is always 0.
Type
R/W
R/W
R/W
R/W
R/W
NA
R
Validity Configuration of S/PDIF Output (VCFG)
Reserved
S/PDIF Configuration Valid (SPCV)
Reserved
SPSA[1:0], S/PDIF Slot Assignment when DRS=0
SPSA[1:0], S/PDIF-Out Slot Assignment when DRS=1(for 96K S/PDIF-Out)
Reserved
SPDIF 1: Enable 0: Disable (SPDIFO is in high impedance)
DRA
VRA
Combines with MX3A.15 to decide validity control in S/PDIF output signal.
0: Current S/PDIF configuration {SPSA, SPSR,DAC/slot rate} is not valid.
1: Current S/PDIF configuration {SPSA, SPSR,DAC/slot rate} is valid.
00: S/PDIF source data assigned to AC-LINK slot3/4
01: S/PDIF source data assigned to AC-LINK slot7/8 (Default when ID=00)
10: S/PDIF source data assigned to AC-LINK slot6/9 (Default when ID=01,10)
11: S/PDIF source data assigned to AC-LINK slot10/11 (Default when ID=11)
01: S/PDIF-Out source is from AC-LINK slot 3/4 + slot 7/8.
1: Enable 0: Disable
1: Enable 0: Disable
17
Function
ALC203 DataSheet
Rev1.6