alc203-lf Realtek Semiconductor Corporation, alc203-lf Datasheet - Page 33

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alc203-lf

Manufacturer Part Number
alc203-lf
Description
Two-channel Ac?97 2.3 Audio Codec
Manufacturer
Realtek Semiconductor Corporation
Datasheet

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7.2.3 AC-Link Clocks
7.2.4 Data Output and Input Timing
Two-Channel AC’97 2.3 Audio Codec
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BIT_CLK high pulse width (note 2)
BIT_CLK low pulse width (note 2)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Note 1: Worse case duty cycle restricted to 45/55.
Output Valid Delay from rising
edge of BIT_CLK
Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
Note 2: 50pF external load
Input Setup to falling edge of
BIT_CLK
Input Hold from falling edge of
BIT_CLK
Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
BIT_CLK combined rise or fall
plus flight time
SDATA combined rise or fall plus
flight time
Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes.
Parameter
Parameter
Parameter
Parameter
SDATA-OUT
SDATA-IN
SYNC
BITCLK
T
T
T
Symbol
Symbol
Symbol
Symbol
T
T
T
sync_period
clk_period
sync_high
sync_low
clk_high
t
clk_low
t
setup
t
hold
Data Output and Input timing diagram
co
Minimum
Minimum
Minimum
Minimum
TsetupThold
36
36
10
10
-
-
-
-
-
-
-
-
-
-
29
V
IL
Typical
Typical
Typical
Typical
12.288
81.4
40.7
40.7
48.0
20.8
19.5
1.3
-
-
-
-
-
-
Maximum
Maximum
Maximum
Maximum
750
ALC203 DataSheet
45
45
15
7
7
-
-
-
-
-
-
-
-
Units
Units
Units
Units
MHz
KHz
µs
µs
µs
ns
ps
ns
ns
ns
ns
ns
ns
ns
Rev1.6

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