alc203-lf Realtek Semiconductor Corporation, alc203-lf Datasheet - Page 38

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alc203-lf

Manufacturer Part Number
alc203-lf
Description
Two-channel Ac?97 2.3 Audio Codec
Manufacturer
Realtek Semiconductor Corporation
Datasheet

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9. Design Suggestions
9.1 Clocking
The clock source is decided by XTLSEL and ID0# latched from pin-46/45 when power-on reset and AC97_RESET# trailing
edge. The clock source of different configuration is listed below:
*Low: Pulled low by a 0 ohm resistor. NC: Not connected or pulled high. X: Don’t care
**Pin-46 and pin-45 are internally pulled high by weak resistors.
Two-Channel AC’97 2.3 Audio Codec
According to AC’97 ver 2.3, the primary mode while RESET# is asserted, if a clock is present at BIT-CLK pin for at least 5
Standard secondary mode, ALC203 receive external 12.288MHz clock from BIT-CLK pin.
cycles before RESET# is de-asserted, ALC203 is a consumer of BITCLK. ALC203 should use external 12.288MHz BITCLK
as its clock source.
ALC203 E version and later versions do not support secondary mode as pin-45 is re-defined as Jack-Detect pin 0 (JD0) for
auto MIC jack sensing.
Configuration
Pin-46(XTLSEL) / 45(ID0#) ID0
Low / Low
Low / NC
NC / NC
NC / NC
X / Low
Operation & ID0
11 (Secondary) Input
1 (Secondary) Input
0 (Primary)
0 (Primary)
0 (Primary)
BIT-CLK
Output
12.288MHz
Output
12.288MHz
Input
34
Clock source
Crystal or ext. 24.576MHz is attached
at XTL-IN
Crystal or ext. 14.318MHz is attached
at XTL-IN
12.288M input at BIT-CLK
12.288M input at BIT-CLK
12.288M input at BIT-CLK
ALC203 DataSheet
Rev1.6

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