k7q161882a-fc15 Samsung Semiconductor, Inc., k7q161882a-fc15 Datasheet - Page 10

• Manufacturer Part Number: k7q161882a-fc15
• Description: 512kx36 & 1mx18 Qdr B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7Q161882A
K7Q163682A
Note: For power-up, V
OPERATING CONDITIONS
AC TIMING CHARACTERISTICS
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
Overershoot Timing
Clock
Clock Cycle Time(K, K, C, C)
Clock HIGH time (K, K, C, C)
Clock LOW time (K, K, C, C)
Clock to clock (K
Clock to data clock (K
Output Times
C, C High to Output Valid
C, C High to Output Hold
C High to Output High-Z
C High to Output Low-Z
Setup Times
Address valic to K rising edge
Control inputs valid to K rising edge
Data-in varid to K, K rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
Supply Voltage
Reference Voltage
Ground
V
DDQ
2. Control signales are R, W,BW
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX
The specs as shown do not imply bus contention beacuse tCHQX
(0 C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70 C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
V
+0.5V
V
IL
DDQ
PARAMETER
PARAMETER
IH
V
DDQ
K , C
20% t
+0.3V and V
C , K
KHKH
C )
0
,BW
(MIN)
C )
DD
(0 C
1
and (BW
1.7V and V
SYMBOL
t
t
t
t
t
t
t
t
t
CHQX1
t
t
t
t
(V
t
t
KHKH
KHKH
KHCH
CHQV
CHQX
CHQZ
AVKH
DVKH
KHAX
KHDX
KHKL
KLKH
T
IVKH
KHIX
2
A
DD
, BW
=1.8V 0.1V, T
DDQ
70 C)
SYMBOL
3
, also for x36)
V
V
V
V
DDQ
REF
1.4V for t
DD
SS
MIN
6.7
2.7
2.7
3.0
0.0
1.2
1.2
0.7
0.7
0.7
0.7
0.7
0.7
-15
- 10 -
512Kx36 & 1Mx18 QDR
1
is a MIN parameter that is worst case at totally different test conditions
MAX
1
200ms
3.7
2.2
2.7
2.7
Undershoot Timing
A
is bigger than tCHQZ.
=0 C to +70 C)
V
SS
-0.5V
MIN
7.5
3.0
3.0
3.4
0.0
1.2
1.2
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IH
SS
MIN
0.68
1.7
1.4
0
-13
MAX
4.1
2.5
3.0
3.0
20% t
MIN
3.5
3.5
4.6
0.0
1.2
1.2
1.0
1.0
1.0
1.0
1.0
1.0
10
MAX
0.95
1.9
1.9
KHKH
-10
0
(MIN)
MAX
5.4
3.0
3.0
3.0
TM
UNITS
b2 SRAM
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
v
UNIT
V
V
V
V
July 2002
NOTES
Rev 1.0
3
3
3
3
2