k7q161882a-fc15 Samsung Semiconductor, Inc., k7q161882a-fc15 Datasheet - Page 6

• Manufacturer Part Number: k7q161882a-fc15
• Description: 512kx36 & 1mx18 Qdr B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7Q161882A
K7Q163682A
Write Operations
Programmable Impedance Output Buffer Operation
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with following K clock.
For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.
The first "early" data is transfered and registered in to the device synchronous with same K clock rising edge with W presented.
Next burst data is transfered and registered synchronous with following K clock rising edge.
Continuous write operations are initiated with K rising edge.
And "early writed" data is presented to the device on every rising edge of both K and K clocks.
When the W is disabled, the K7Q163682A and K7Q161882A will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7Q163682A and K7Q161882A support byte write operations.
With activating BW
In K7Q161882A, BW
And in K7Q163682A BW
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs"
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently
Before chip deselected, all read and write pending operations are completed.
Single Clock Mode
The K7Q163682A and K7Q161882A can be used with the single clock pair K and K.
In this mode, C and C must be tied high during power up and this single clock pair control both the input and output registers.
C and C cannot be tied high during operation.
System flight time and clock skew could not be compensated in single clock mode.
or other anomalous behavior in the SRAM.
the SRAM needs 1024 non-read cycles.
and read and write operation do not affect each other.
0
resistor will give an output impedance of 50 .
or BW
0
controls write operation to D0:D8, BW
2
1
controls write operation to D18:D26, BW
( BW
2
or BW
3 )
in write cycle, only one byte of input data is presented.
1
controls write operation to D9:D17.
- 6 -
512Kx36 & 1Mx18 QDR
3
controls write operation to D27:D35.
SS
through a precision resistor(RQ).
TM
b2 SRAM
July 2002
Rev 1.0