k7q161882a-fc15 Samsung Semiconductor, Inc., k7q161882a-fc15 Datasheet - Page 7

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k7q161882a-fc15

Manufacturer Part Number
k7q161882a-fc15
Description
512kx36 & 1mx18 Qdr B2 Sram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
K7Q163682A
TM
K7Q161882A
512Kx36 & 1Mx18 QDR
b2 SRAM
STATE DIAGRAM
POWER-UP
READ
WRITE
READ NOP
WRITE NOP
READ
WRITE
LOAD NEW
LOAD NEW
WRITE
READ
READ ADDRESS
WRITE ADDRESS
ALWAYS
ALWAYS
READ
WRITE
(FIXED)
(FIXED)
WRITE PORT NOP
DDR READ
DDR WRITE
Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.
2. "READ" refers to read active status with R=Low, "READ" refers to read inactive status with R=high. "WRITE" and "WRITE" are the same case.
3. Read and write state machine can be active simultaneously.
4. State machine control timing sequence is controlled by K.
July 2002
- 7 -
Rev 1.0

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