k7q161882a-fc15 Samsung Semiconductor, Inc., k7q161882a-fc15 Datasheet - Page 4

• Manufacturer Part Number: k7q161882a-fc15
• Description: 512kx36 & 1mx18 Qdr B2 Sram
• Manufacturer: Samsung Semiconductor, Inc.

K7Q161882A
K7Q163682A
PIN NAME
Notes: 1. C, C, K or K cannot be set to V
PIN CONFIGURATIONS
Notes : 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 9A for 32Mb, 3A for 64Mb, 10A for 128Mb and 2A for 256Mb.
BW
M
A
B
C
D
E
G
H
K
N
P
R
F
J
L
0
, BW
2. When ZQ pin is directly connected to V
3. Not connected to chip pad internally.
SYMBOL
2. BW
D0-35
Q0-35
V
V
TMS
TDO
C, C
TCK
K, K
V
V
TDI
SA
ZQ
NC
1,
DDQ
W
REF
R
DD
SS
BW
TDO
Q27
D27
D28
Q29
Q30
D30
D31
Q32
Q33
D33
D34
Q35
0
NC
NC
1
controls write to D0:D8, BW
2
, BW
3
V
SS
V
TCK
Q18
Q28
D20
D29
Q21
D22
Q31
D32
Q24
Q34
D26
D35
REF
2
/SA*
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
NC/SA*
6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
(TOP VIEW)
V
D18
D19
Q19
Q20
D21
Q22
D23
Q23
D24
D25
Q25
Q26
SA
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
DDQ
REF
3
1C,1D,2E,1G,1J,2K,1M,1N,2P
2A,10A,4C,8C,4D-8D,5E-7E,
1
voltage.
controls write to D9:D17, BW
DD
1A,3A,9A,11A,1H
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
PIN NUMBERS
V
V
V
V
V
V
V
7B,7A,5A,5B
V
V
V
V
SA
SA
SA
W
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
4
SS
SS
SS
SS
2H,10H
6P, 6R
6B, 6A
11H
10R
11R
4A
8A
2R
1R
K7Q163682A(512Kx36)
BW
BW
V
V
V
V
V
V
V
V
V
SA
SA
SA
SA
5
SS
SS
DD
DD
DD
DD
DD
SS
SS
2
3
- 4 -
2
512Kx36 & 1Mx18 QDR
controls write to D18:D26 and BW
V
V
V
V
V
V
V
V
V
SA
SA
K
K
C
C
6
SS
SS
SS
SS
SS
SS
SS
SS
SS
BW
BW
V
V
V
V
V
V
V
V
V
SA
SA
SA
SA
7
SS
SS
DD
DD
DD
DD
DD
SS
SS
Output Driver Impedance Control Input
1
0
Output Power Supply (1.5V or 1.8V)
Input Clocks for Output data
Input Reference Voltage
V
V
V
V
V
V
V
JTAG Test Mode Select
JTAG Test Data Output
V
V
V
V
Power Supply ( 1.8 V )
Byte Write Control Pin
SA
SA
SA
JTAG Test Data Input
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
R
8
SS
SS
SS
SS
Read Control Pin
Write Control Pin
JTAG Test Clock
DESCRIPTION
Address Inputs
Data Outputs
No Connect
3
Data Inputs
Input Clock
controls write to D27:D35.
Ground
NC/SA*
V
D17
D16
Q16
Q15
D14
Q13
D12
Q12
D11
D10
Q10
Q9
SA
DDQ
9
TM
V
SS
V
TMS
Q17
D15
Q14
D13
Q11
Q7
D6
Q4
D3
Q1
D9
D0
10
REF
b2 SRAM
/SA*
July 2002
NOTES
Rev 1.0
TDI
NC
ZQ
Q8
D8
D7
Q6
Q5
D5
D4
Q3
Q2
D2
D1
Q0
11
1
2
3