UPD16488AP NEC [NEC], UPD16488AP Datasheet - Page 16

• Manufacturer Part Number: UPD16488AP
• Description: 1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
• Manufacturer: NEC [NEC]

5.1.3 Serial interface
serial clock input (SCL) can be received. Serial data is read from D
clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to
parallel data for processing. RS input is used to judge serial input data as display data or command data: when RS = H the
data is display/command data and when RS = L the data is index data. When the chip enters active mode, RS input is read
at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal
chart is shown below.
5.1.4 Chip select
when /CS1 = L and CS2 = H. When chip select is inactive, P
or /WR is not active. If serial interface mode has been set, the shift register and counter are both reset.
5.1.5 Display data RAM and on-chip register access
transfer is possible. There is no need to consider any wait time. No dummy data is needed when writing data. Even when
data is read, there is no need for dummy data except in the display memory access register (R11).
When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI) and
The PD16488A has two chip select pins (/CS1 and CS2). The CPU parallel interface or serial interface can be used only
Because only the required cycle time (t
In other words, dummy data is required only when reading data from the display memory access register (R11).
Figure 5-2 illustrates this relationship.
16
Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings.
CS2 = H
/CS1
SCL
RS
SI
2. The data read function is disabled during serial interface mode.
3. When using SCL wiring, take care concerning the possible effects of terminating reflection and
noise from external sources. We recommend checking operation with the actual device.
D
1
7
D
2
6
D
3
5
D
4
Figure 5-1. Serial Interface Signal Chart
4
cyc
) is satisfied when accessing the PD16488A from the CPU, high-speed data
D
5
3
Data Sheet S15745EJ2V0DS
D
6
2
D
7
1
0
D
8
to P
0
7
D
9
are set to high impedance (invalid) and input of RS, /RD,
7
7
and then from D
D
10
6
D
11
5
D
12
4
6
to D
D
13
3
0
on the rising edge of the serial
D
14
2
D
15
1
16
D
0
D
17
7
PD16488A
18
D
6