UPD16488AP NEC [NEC], UPD16488AP Datasheet - Page 64

• Manufacturer Part Number: UPD16488AP
• Description: 1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
• Manufacturer: NEC [NEC]

6.20 Inversion End Line Address Register (R19)
using reverse (inverted) display mode. The range of inverted lines is determined based on the contents of this register and
the inversion start line address register.
Default settings (initial values set by reset command)
6.21 Inverted Data Memory Access Register (R20)
accessed, the data is written directly to the inverted data RAM.
Default settings (initial values set by reset command, all data)
6.22 Partial Start Line Address Register (R21)
partial display mode. The partial display area is determined as the number of lines specified in the partial display mode
setting register (R10), starting from this start line address.
Default settings (initial values set by reset command)
The inversion end line address register specifies the end line address in the display RAM accessed by the CPU when
The inverted data memory access register is used when accessing the inverted data RAM. When this register is
When using reset command to reset, the contents of memory are retained.
The partial start line address register specifies the start line address in the display RAM accessed by the CPU when using
RS
RS
RS
D
D
D
64
1
−
1
0
1
−
7
7
7
Data
0
1
D
D
D
D
D
D
D
−
0
0
−
0
7
6
7
7
6
7
6
Normal
Inverted
PSL6
IEL6
D
D
D
D
D
D
D
0
0
0
6
5
6
6
5
6
5
PSL5
IEL5
Status
D
D
D
D
D
D
D
0
0
0
5
4
5
5
4
5
4
PSL4
IEL4
D
D
D
D
D
D
D
0
0
0
4
3
4
4
3
4
3
PSL3
IEL3
D
D
D
D
D
D
D
Data Sheet S15745EJ2V0DS
0
0
0
3
2
3
3
2
3
2
PSL2
IEL2
D
D
D
D
D
D
D
0
0
0
2
1
2
2
1
2
1
PSL1
IEL1
D
D
D
D
D
D
D
0
0
0
1
0
1
1
0
1
0
PSL0
IEL0
D
D
D
D
0
0
0
0
Setting
Setting
Setting
−
−
−
µ µ µ µ PD16488A