UPD16488AP NEC [NEC], UPD16488AP Datasheet - Page 54

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UPD16488AP

Manufacturer Part Number
UPD16488AP
Description
1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
Manufacturer
NEC [NEC]
Datasheet
6. COMMAND REGISTERS
interpretation and execution is performed using internal timing that does not depend on any external clock. Therefore,
processing is very fast and there is usually no need to check for a busy status.
commands using a low pulse input to the /WR pin. The M68 series CPU interface sets read mode using a high level input
to the R,/W pin and sets write mode using a low level input to the same pin. It activates both read and write commands
using a high-level pulse input to the E pin.
from the i80 series CPU interface in that /RD (E) is at high level during status read and display data read operations, as
shown in the following command descriptions and command table.
The µ PD16488A uses a combination of RS, /RD (E), and /WR (R,/W) signals to identify data bus signals. Command
The i80 series CPU interface activates read commands using a low pulse input to the /RD pin and activates write
Command descriptions using an i80 series CPU interface are shown as follows. The M68 series CPU interface differs
If the serial interface has been selected, data is input sequentially starting from D
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Data Sheet S15745EJ2V0DS
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µ µ µ µ PD16488A

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