kac-9637 ETC-unknow, kac-9637 Datasheet - Page 11

• Manufacturer Part Number: kac-9637
• Description: Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
1.0
1.1
The KAC-9637 contains a CMOS active pixel array consisting of
488 rows by 648 columns. 24 columns of optically shielded
(black) pixels are provided to the right of the array as shown in
Figure 6. Only the middle 8 black columns are used for black
level compensation. The black pixels are physically located at
the end of each row but are read out first.
At the beginning of a given integration time the on-board timing
and control circuit will reset every pixel in the array one row at a
time as shown in Figure 7. Note that all pixels in the same row
are simultaneously reset, but not all pixels in the array.
At the end of the integration time, the timing and control circuit
will address each row and simultaneously transfer the integrated
value of the pixel to a correlated double sampling circuit and
then to a shift register as shown in Figure 7.
Once the correlated double sampled signals have been loaded
into the shift register, the timing and control circuit will shift them
out one pixel at a time.
The analog pixel signal is then fed into an analog gain channel
as shown in figure 8. The gain channel can be digitally pro-
grammed allowing the signal level of pixel to be adjusted.
After gain adjustment the analog value of each pixel is con-
verted to a 10 bit digital data as shown in figure 8.
Figure 7. CMOS APS Row and Column addressing scheme
www.kodak.com/go/imagers 585-722-4385
Light Capture and Conversion
OVERVIEW
Figure 6. CMOS APS region of the KAC-9637
648 columns, 488 rows
Analog Data Out
active pixels
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
a b c d e f g h i
CDS/Shift Register
24 columns
black pixels
j
k l m n o p q r
11
The black level together with the full analog signal path offset is
automatically compensated as shown in figure 8. This can be
manually overridden.
Finally the pixel data is framed and output on the digital video
bus as shown in figure 9.
1.2
The programming, control and status monitoring of the KAC-
9637 is achieved through a two wire I
device address pin is provided allowing two different device
addresses to be selected for the serial interface as shown in Fig-
ure 10.
Figure 8. Analog Signal Conditioning & Conversion to
Register Bank
Program and Control Interfaces
Figure 10. Control Interface to the KAC-9637.
Figure 9. Digital Pixel Processing.
MUX
+/-
Manual Offset
Register
Amp
I
2
Digital
C Compatible
Auto Black Level
Serial I/F
Compensation
Target & Rate
Registers
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2
C compatible serial bus. A
do[9:0]
pclk
hsync
vsync
10 Bit A/D
sda
sclk