kac-9637 ETC-unknow, kac-9637 Datasheet - Page 19

• Manufacturer Part Number: kac-9637
• Description: Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
9.0
The serial bus interface consists of the sda (serial data) and
sclk (serial clock) pins. The KAC-9637 can operate only as a
slave.
The sclk pin is an input, it only controls the serial interface, all
other clock functions within KAC-9637 use the master clock pin,
mclk. Mclk must be running at least 4 times faster than sclk to
write to the serial bus.
9.1
The serial bus will recognize a logic 1 to logic 0 transition on the
sda pin while the sclk pin is at logic 1 as the start condition. A
logic 0 to logic 1 transition on the sda pin while the sclk pin is at
logic 1 is interrupted as the stop condition as shown in Figure
22.
9.2
The Device Address can be changed by writing to the
I2cDevAddr parameter in the I2CMODE Register.
9.3
The KAC-9637 will hold the value of the sda pin to a logic 0 dur-
ing the logic 1 state of the Acknowledge clock pulse on sclk as
shown in Figure 23.
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sda
sclk
sda
sclk
from master
sda
sclk
sda
from sensor
SERIAL BUS
Start/Stop Conditions
Device Address
Acknowledgment
start condition
START
S
S
S
S
Figure 22. Start/Stop Conditions
Device
Address
Figure 23. Acknowledge
MSB
1
MSB
1
2
2
W
S
A
7
Address
Device
7
stop condition
Figure 26. Serial Bus Write Operation
Figure 27. Serial Bus Read Operation
Register
Address
Figure 25. Serial Bus Byte Format
8
Clock pulse
P
for ACK
W
byte complete
8
9
from receiver
A
ack signal
ACK
ACK
ACK
A
9
Register
Address
19
clock line
held low
S
9.4
The master must ensure that data is stable during the logic 1
state of the sclk pin. All transitions on the sda pin can onlyoccur
when the logic level on the sclk pin is “0” as shown in Figure 24
9.5
Every byte consists of 8 bits. Each byte transferred on the bus
must be followed by an Acknowledge. The most significant bit of
the byte is should always be transmitted first. See Figure 25.
9.6
A write operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. When
the master receives an Acknowledge from the sensor it can
transmit an 8-bit internal register address. The sensor will
respond with a second Acknowledge signaling the master to
transmit 8 write data bits. A third Acknowledge is issued by the
sensor when the data has been successfully received.
The write operation is completed when the master asserts a
Stop Condition or a second Start Condition. See Figure 26.
9.7
A read operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. When
the master receives an Acknowledge from the sensor it can
transmit the internal Register Address byte. The sensor will
respond with a second Acknowledge. The master must then
issue a new Start Condition followed by the sensor’s Device
Address and read bit. The sensor will respond with an Acknowl-
edged followed by the Read Data byte.
The read operation is completed when the master asserts a Not
Acknowledge followed by Stop Condition or a second Start Con-
dition. See Figure 27.
9.8
Several addresses can be written to without the need to re-start
by setting the AdvWr bit in the I2CMODE register to a logic 1.
sda
sclk
Address
A
Device
Data Valid
Byte Format
Write Operation
Read Operation
Advanced Write Mode
1
Data
Byte
data valid
data line
stable;
2
Figure 24. Data Validity
R
A
P
A
change
of data
allowed
8
Data
Byte
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ACK
bold sensor action
9
data valid
data line
from receiver
bold sensor action
stable;
ack signal
_
A
P
P