kac-9637 ETC-unknow, kac-9637 Datasheet - Page 23

• Manufacturer Part Number: kac-9637
• Description: Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
10.5
By default the sensor’s digital video port synchronisation signals
are configured to operate in slave mode. In slave mode the inte-
grated timing and control block will only start frame and row pro-
cessing upon the receipt of triggers from an external source.
Note:
Only two synchronization signals are used in slave mode as fol-
lows:
Figure 41 shows the KAC-9637’s digital video port in slave
mode connected to a digital video processor master DVP.
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1. Partial frame integration is disabled in slave mode.
2. In order to get all rows out of the device in slave mode
VsynPol and HsynPol bits of register 0x53h must be set to
0.
hsync
vsync
(frame trigger)
(row trigger)
internal row
Synchronisation Signals in Slave Mode
counter
hsync
vsync
mclk
KAC-9637
Figure 41. KAC-9637 in slave mode
(row trigger)
is the row trigger input signal.
is the frame trigger input signal.
d[9:0]
hsync
vsync
hsync
d[9:0]
mclk
mclk
pclk
Figure 42. hsync slave mode timing diagram for centered display window of 640 pixels
Minimum Valid Hsync Pulse Width
96 mclk clock cycles
(continued)
din[9:0]
RowTrig
FrameTrig
Pixel Clock
MasterClock
DVP
Figure 43. vsync slave mode timing diagram.
Last Row of Current Frame
X
mclk
First Pixel In The Row
23
10.6
The row trigger input pin, hsync, is used to trigger the process-
ing of a given row. It must be activated for at least two mclk
cycles. The first pixel data will appear at d[9:0] “X
after the falling edge of the row trigger, where X
Where:
The polarity of the active level of the row trigger can be pro-
grammed using the HsynPol bit of the DVBUSCONFIG1 regis-
ter. By default it is active high.
10.7
The frame trigger input pin, vsync, is used to reset the row
address counter and prepare the array for row processing. It
must be activated for at least one more mclk cycle than the row
trigger and the falling edge must be between 1 and 96 mclk
cycles after falling edge of hsync as illustrated in Figure 43.
The polarity of the active level of the frame trigger is program-
mable. By default it is active high.
PrtFrmEn is the partial frame integration bit setting in the
BlkPixelEn
Row Trigger Input Pin (hsync)
Frame Trigger Input Pin (vsync)
Number Of Pixel In The Row
X
mclk
= 146 + PrtFrmEn*37 - 8*BlkPixelEn
ITIMECONFIG register.
is the BlkPixelEn bit setting in the
DVBUSCONFIG2 register
First Row of Next Frame
Last Pixel In The Row
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mclk
is given by:
mclk
“periods