kac-9637 ETC-unknow, kac-9637 Datasheet - Page 17

• Manufacturer Part Number: kac-9637
• Description: Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
6.4
Full frame integration is when each pixel in the array integrates
light incident on it for the duration of a frame (see Figure 20).
The number of pixels processed per row is given by:
Where:
The number of Hclk clock cycles required to process & shift out
one row of pixels is given by:
Where:
The number of rows in the active window is given by:
Where:
.
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WEndCol
WStartCol
R
R
N
MH
R
WEndRow
RN
opcycle
Itime
pix
delay
Row n
Full Frame Integration
N
factor
Hclk
rows
= R
= (WEndRow - WStartRow + 1) * MV
N
is the “Active Window” column start address as
programmed in registers WCOLE and WCOL-
LSB.
is the “Active Window” column end address as
programmed in registers WCOLS and WCOL-
LSB.
is a fixed integer value of 137 representing the
Row Operation Cycle Time in multiples of Hclk
clock cycles. It is the time required to carry out
all fixed row operations outlined in Figure 17.
When partial frame integration is enabled, (Prt-
FrmEn bit in the ITIMECONFIG register is set to
a logic 1), R
Partial frame integration is disabled, (PrtFrmEn
bit in the ITIMECONFIG register is set to a logic
0), R
Is the number of pixels processed in a row.
Is 1 when horizontal subsampling is disabled
and 0.5 when horizontal subsampling is
enabled.
a programmable value between 0 & 8191 repre-
senting the Row Delay Time in multiples of Hclk.
This parameter allows the Row Operation Cycle
time to be extended. The Rdelay value is pro-
grammed in the RDELAYH and RDELAYL regis-
ters.
is the “Active Window” row start address as pro-
grammed in registers WROWE and WROWLSB.
Frame
pix
opcycle
Delay
= WEndCol - WStartCol + 1
Itime
+ R
is a fixed integer of 0.
Row 0
Itime
Itime
is a fixed integer of 37. When
+ (N
pix
Row 1
(continued)
Programmable Row Delay
Programmable Row Delay
*MH
Figure 20. Partial and Full Frame Integration
factor
Row 2
) + R
factor
delay
Partial Frame Integration
Full Frame integration
Full Integration Time
17
Row x
Row CDS, Reset Row x+∆ & Shift
Row CDS, Reset Row x & Shift
The number of Hclk clocks required to process a full frame is
given by:
Where:
The frame rate is given by:
6.5
In some cases it is desirable to reduce the time during which the
pixels in the array are allowed to integrate incident light without
changing the frame rate.
This is known as Partial Frame Integration and can be achieved
by resetting pixels in a given row ahead of the row being
selected for readout as shown in Figure 20. The number of Hclk
clocks required to process a partial frame is given by:
Where:
Note:
Upon system reset the partial frame integration is automatically
enabled. It can be disabled by setting the PrtFrmEn bit in the
ITIMECONFIG register to a logic 0 or by programming 0.
Partial Integration
WStartRow
MV
N
F
RN
Itime
delay
rows
Partial Frame Integration
Hclk
factor
Time
FN
is the “Active Window” row end address as pro-
grammed in registers WROWS and WROWLSB.
is 1 when vertical subsampling is disabled and
0.5 when vertical subsampling is enabled.
Hclk
is the number of rows in the “Active Window”.
a programmable value between 0 & 32766 rep-
resenting the Inter Frame Delay in multiples of
RN
be extended. (See the Frame Delay High and
Frame Delay Low registers). The Fdelay value is
programmed in the FDELAYH and FDELAYL
registers.
is the number of Hclk clock cycles required to
process & shift out one row of pixels.
a programmable value between 0 & 32767 rep-
resenting the number of rows ahead of the cur-
rent row to be reset. This value must not be
larger than the number of active rows. The Itime
value is programmed in the ITIMEH and ITIMEL
registers.
FP
Hclk
Row x+∆ Row n
= [N
Frame Rate =
Hclk
. This parameter allows the frame time to
rows
= RN
+ Fdelay]
Hclk *
FN
Hclk
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Itime
Hclk
*
Frame
Delay
RN
Hclk
Row 0