sii3114 Silicon image, sii3114 Datasheet - Page 35

• Manufacturer Part Number: sii3114
• Description: Pci To Serial Ata Controller
• Manufacturer: Silicon image

Silicon Image, Inc.
PCI Status – PCI Command
Address Offset: 04
Access Type: Read/Write/Write-One-to-Clear
Reset Value: 0x02B0_0000
This register defines the various control functions associated with the PCI bus. The register bits are defined
below.
© 2007 Silicon Image, Inc.
• Bit [31] : Det. Par Err (R/W1C) – Detected Parity Error. This bit set indicates that the SiI3114 detected a
• Bit [30] : Sig. Sys Err (R/W1C) – Signaled System Error. This bit set indicates that the SiI3114 signaled
• Bit [29] : Rcvd M Abort (R/W1C) – Received Master Abort. This bit set indicates that the SiI3114 terminated
• Bit [28] : Rcvd T Abort (R/W1C) – Received Target Abort. This bit set indicates that the SiI3114 received a
• Bit [27] : Sig. T Abort (R/W1C) – Signaled Target Abort. This bit set indicates that the SiI3114 terminated a
• Bit [26:25] : Devsel Timing (R) – Device Select Timing. This bit field indicates the DEVSEL timing supported
• Bit [24] : Det M Data Par Err (R/W1C) – Detected Master Data Parity Error. This bit set indicates that the
• Bit [23] : Fast B-to-B Capable (R) – Fast Back-to-Back Capable. This bit is hardwired to 1 to indicate that
• Bit [22] : Reserved (R).
• Bit [21] : 66 MHz Capable (R) – 66 MHz PCI Operation Capable. This bit is hardwired to 1 to indicate that
• Bit [20] : Capabilities List (R) – PCI Capabilities List. This bit is hardwired to 1 to indicate that the SiI3114
• Bit [19] : Interrupt Status (R)
• Bit [18:11] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [10] : Interrupt Disable (R/W).
• Bit [09] : Fast B-to-B Enable (R) – Fast Back-to-Back Enable. This bit is hardwired to 0 to indicate that the
• Bit [08] : SERR Enable (R/W) – SERR Output Enable. This bit set enables the SiI3114 to drive the PCI
• Bit [07] : Address Stepping (R) – Address Stepping Enable. This bit is hardwired to 0 to indicate that the
• Bit [06] : Par Error Response (R/W) – Parity Error Response Enable. This bit set enables the SiI3114 to
• Bit [05] : VGA Palette (R) – VGA Palette Snoop Enable. This bit is hardwired to 0 to indicate that the
• Bit [04] : Mem Wr & Inv (R) – Memory Write and Invalidate Enable. This bit is hardwired to 0 to indicate that
parity error on the PCI bus-address or data parity error-while responding as a PCI target.
SERR on the PCI bus.
a PCI bus operation with a Master Abort.
Target Abort termination.
PCI bus operation with a Target Abort.
by the SiI3114. The hardwired value is 01
SiI3114, as bus master, detected a parity error on the PCI bus. The parity error may be either reported by
the target device via PERR# on a write operation or by the SiI3114 on a read operation.
the SiI3114 is Fast Back-to-Back capable as a PCI target.
the SiI3114 is 66 MHz capable.
has a PCI Power Management Capabilities register linked at offset 34
SiI3114 does not support Fast Back-to-Back operations as bus master.
SERR# pin when it detects an address parity error. The Parity Error Response bit (06) must also be set to
enable SERR# reporting.
SiI3114 does not support Address Stepping.
respond to parity errors on the PCI bus. If this bit is cleared, the SiI3114 will ignore PCI parity errors.
SiI3114 does not support VGA Palette Snooping.
the SiI3114 does not support Memory Write and Invalidate.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
H
B
for Medium decode timing.
27
Reserved
H
.
SiI3114 PCI to Serial ATA Controller
SiI-DS-0103-D
Data Sheet