sii3114 Silicon image, sii3114 Datasheet - Page 79

• Manufacturer Part Number: sii3114
• Description: Pci To Serial Ata Controller
• Manufacturer: Silicon image

Silicon Image, Inc.
Serial ATA PHY Configuration
Address Offset: 144
Access Type: Read/Write
Reset Value: 0x2000_80B0
The PHY Configuration register is auto-initialized from external flash or EEPROM. The bit definitions are as
follows:
© 2007 Silicon Image, Inc.
• Bit [20] : Cont_dis (R/W)– Setting this bit disables the CONT primitive, i.e., the SiI3114 will always send the
• Bit [19] : VS_Lock_Abort (R/W)– This bit controls the changes to the entries in the Command Protocol
• Bit [18] : fpdmawr (W)– Setting this bit initiates a DMA write transfer
• Bit [17] : dmainen(R/W)– This bit enables Read DMA operations for First Party DMA or transparent FIS
• Bit [16] : dmaouten (R/W)– This bit enables Write DMA operations for First Party DMA or transparent FIS
• Bit [15] : Reserved (R/W). This bit is reserved and returns zero on a read. Always write 0 to these bits.
• Bit [14] : devdrvn (R/W) – This bit enables the protocol to be solely determined by FISes from the device.
• Bit [13] : nienfis_dis (R/W)– If this bit is set, a Control Register FIS will not be sent in response to a change
• Bit [12] : Reserved (W). Always write 0 to these bits.
• Bit [11] : ComWake/Clear_BSY (R/W)– When the Serial ATA interface is in PARTIAL or SLUMBER mode,
• Bit [10:09] : pm_fiscfg[1:0] (R/W)– Configuration for interpreting FISes with a different Port Multiplier port
• Bit [08] : pm_locken (R/W)– If set, no SYNC is sent after a DMA Activate FIS, a PIO Setup FIS for PIO Out,
• Bit [07] : regfismode (R/W) – If set, received Register FIS will not be used to update task file if BSY = DRQ
• Bit [06] : PMCHG (R/W1C)– This bit reports a change in the Power Management mode. This bit
• Bit [05:04] : PMMODE (R)– These bits report the power management mode status: bit 5 corresponds to
• Bit [03:02] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [01:00] : PMREQ (W) – These bits initiate power management requests: setting bit 1 will send a
• Bit[31:22] : Reserved. The values of these bits should not be changed from their defaults otherwise erratic
• Bit[21] : Bypass OOB sequence. If the bit set to 1, all channel Tx outputs random pattern data.
• Bit[20] : Reserved. The value of this bits should not be changed from their defaults otherwise erratic
• Bit[19] : Tx_Swing_1: This bit, together with Tx_Swing_0, sets the nominal output amplitude for the
actual primitive instead of a CONT followed by random data.
Table upon receiving a VS_Lock command. If this bit is set, all Command Protocol Table will be cleared. If
this bit is not set, the Command Protocol Table will not be cleared in the VS_Lock state.
operation.
operation.
in nIEN.
setting this bit (to 1) asserts ComWake on the Serial ATA bus. When the Serial ATA interface is ON and an
interlocked FIS is received, setting this bit (to 1) clears BSY in the ATA Status.
number from that specified in SControl.
or an interlocked FIS when dmaouten (bit 16) is set.
= 0.
corresponds to the interrupt enabled by bit 26 of SIEN. This bit is cleared by writing a 1.
Slumber mode; bit 4 to Partial mode. A transition on either of these bits causes a Power Management
mode change interrupt.
Slumber mode request to the device; setting bit 0 will send a Partial mode request to the device.
operation may result
operation may result
Transmitter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
H
Reserved
71
8
SiI3114 PCI to Serial ATA Controller
7
Reserved
6
5
4
3
2
1
SiI-DS-0103-D
0
Data Sheet