sii3114 Silicon image, sii3114 Datasheet - Page 50

• Manufacturer Part Number: sii3114
• Description: Pci To Serial Ata Controller
• Manufacturer: Silicon image

SiI3114 PCI to Serial ATA Controller
Data Sheet
Internal Register Space – Base Address 2
Access to these registers is modified by the “shadow” Channel 1/3 Device Select bit. The “shadow” Channel 1/3
Device Select bit is written from bit 4 of the byte written to the Channel 1/3 Task File Device+Head register (offset
06
These registers are 32-bits wide and define the internal operation of the SiI3114. The access types are defined as
follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O
space. Table 19 shows the internal register space for base 2 addresses.
Channel 1/3 Task File Register 0
Address Offset: 00
Access Type: Read/Write
Reset Value: 0x0000_0000
This register defines four of the Channel 1/3 Task File registers in the SiI3114. The register bits are also mapped
to Base Address 5, Offset C0
value in the “shadow” Channel 1/3 Device Select bit is used to select the Task File registers for either Channel 1
(Master; bit is 0) or Channel 3 (Slave; bit is 1).
Channel 1/3 Task File Register 1
Address Offset: 04
Access Type: Read/Write
Reset Value: 0x0000_0000
This register defines four of the Channel 1/3 Task File registers in the SiI3114. The register bits are also mapped
to Base Address 5, Offset C4
for writing the Device+Head Task File register, the value in the “shadow” Channel 1/3 Device Select bit is used to
select the Task File registers for either Channel 1 (Master; bit is 0) or Channel 3 (Slave; bit is 1). For writing the
Device+Head Task File register, the value being written to bit 4 of the register (the Device Select bit) is used to
select the Task File register for either Channel 1 (Master; bit is 0) or Channel 3 (Slave; bit is 1); a 0 is always
SiI-DS-0103-D
H
).
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Address
Offset
00
04
Starting Sector Number
H
H
Command + Status
H
H
Command+Status
31
Starting Sector
Number
Table 19. SiI3114 Internal Register Space – Base Address 2
H
H
. See “Channel X Task File Register 0” section on page 62 for bit definitions. The
. See “Channel X Task File Register 1” section on page 62 for bit definitions. Except
Sector Count
Device+Head
Device+Head
Sector Count
Register Name
Data (dword access)
16
42
15
Cylinder High
Features (W)
Features (W) Error (R)
Error (R)
Cylinder High
Data (word access)
Cylinder Low
Data
Data (byte access)
Cylinder Low
00
© 2007 Silicon Image, Inc.
Silicon Image, Inc.
Access
Type
R/W
R/W