sii3114 Silicon image, sii3114 Datasheet - Page 95

• Manufacturer Part Number: sii3114
• Description: Pci To Serial Ata Controller
• Manufacturer: Silicon image

Silicon Image, Inc.
Table 31 shows the default configurations of all Serial ATA FIS types.
RxFIS[0-6]- First seven dwords received from device. RxFIS[0] is the first dword that contains the FIS header.
RxFIS[6] is the last of the seven dwords received. It is enough to support DMA Setup FIS.
Note that:
The following summarizes the behavior:
© 2007 Silicon Image, Inc.
Others reserved
Code
A1h
A6h
B8h
BFh
C7h
D4h
D9h
27h
34h
39h
41h
46h
58h
5Fh
FIS
• FIS data can also be read out directly from RxFIS (first seven dwords).
• All data to be transferred must be sent within one UDMA burst. Burst termination will not be allowed and
• There is no limit on received frame size.
• In a Data FIS, the receive FIFO will automatically advance one dword to skip the header. Upon an
On power up, the default configurations are as follows:
Sequences:
may produce unpredictable result.
interlocked FIS, the FIFO read pointer will rewind to the beginning so that the first dword read is the
header.
• All defined FISes, except BIST Activate and DMA Setup, default to be supported (FISxxcfg[1:0] = '00').
• BIST Activate is default to be accepted ONLY for Far-end Retimed Loopback and to be rejected for any
• DMA Setup defaults to be rejected.
• All undefined FISes default to be rejected (FISxxcfg[1:0] = '01').
•
•
Register (Host to Device)
Register (Device to Host)
DMA Activate
DMA Setup
Data
BIST Activate
PIO Setup
Set Device Bits
reserved
reserved
reserved
reserved
reserved
reserved
FIS Name
other BIST types.
Upon reception of an unsupported FIS (FISxxcfg[1:0] = '01'), the Link/Transport Logic responds with
R_ERR to the downstream device. The host will not be notified.
Upon reception of a supported FIS (FISxxcfg[1:0] = '00'), the Link/Transport Logic responds with
R_OK at WTRM (if no error is detected) or R_ERR (if an error is detected) to the downstream device.
The host will be notified only as required by the protocol.
Register Bits
FIS5Fcfg[1:0]
FISbFcfg[1:0]
FIS27cfg[1:0]
FIS34cfg[1:0]
FIS39cfg[1:0]
FIS41cfg[1:0]
FIS46cfg[1:0]
FIS58cfg[1:0]
FISa1cfg[1:0]
FISa6cfg[1:0]
FISb8cfg[1:0]
FISc7cfg[1:0]
FISd4cfg[1:0]
FISd9cfg[1:0]
FISocfg[1:0]
Table 31. Default FIS Configurations
Configuration Bits
Default Value
87
00b
00b
00b
00b
00b
01b
01b
01b
01b
01b
01b
01b
01b
01b
00b
Comments
Default to reject FIS without interlock.
Default to accept FIS without interlock.
Default to accept FIS without interlock.
Default to reject.
Default to accept FIS without interlock.
Default to accept for far-end retimed loopback,
reject for any other.
Default to accept FIS without interlock.
Default to accept FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
Default to reject FIS without interlock.
SiI3114 PCI to Serial ATA Controller
SiI-DS-0103-D
Data Sheet