sii3114 Silicon image, sii3114 Datasheet - Page 74

• Manufacturer Part Number: sii3114
• Description: Pci To Serial Ata Controller
• Manufacturer: Silicon image

SiI3114 PCI to Serial ATA Controller
Data Sheet
Data Transfer Mode – Channel X
Address Offset: B4
Access Type: Read/Write
Reset Value: 0x0000_0022
This register defines the transfer mode register for Channel 0 in the SiI3114. The register bits are defined below.
SiI-DS-0103-D
• Bit [15] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [14] : Watchdog Int Ena (R/W) – Channel X Watchdog Interrupt Enable. This bit is set to enable an
• Bit [13] : Watchdog Ena (R/W) – Channel X Watchdog Timer Enable. This bit is set to enable the watchdog
• Bit [12] : Watchdog Timeout (R/W1C) – Channel X Watchdog Timer Timeout. This bit set indicates that the
• Bit [11] : Interrupt Status (R) – Channel X Interrupt Status. This bit set indicates that an interrupt is pending
• Bit [10] : Virtual DMA Int (R) – Channel X Virtual DMA Completion Interrupt. This bit set indicates that the
• Bit [09:03] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [02] : Channel Rst (R/W) – Channel X Reset. When this bit is set, Channel X RST signal is asserted.
• Bit [01] : Buffered Cmd (R) – Channel X Buffered Command Active. This bit set indicates that a Buffered
• Bit [00] : Reserved (R). This bit is reserved and returns one on a read.
• Bit [31:08] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [07:06] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [05:04] : Device 1 Transfer Mode (R/W) – Channel X Device 1 Data Transfer Mode. This bit field is used
• Bit [03:02] : Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [01:00] : Device 0 Transfer Mode (R/W) – Channel X Device 0 Data Transfer Mode. This bit field is used
interrupt when the Watchdog timer expires.
timer for Channel X . This bit is cleared to disable the watchdog timer.
watchdog timer for Channel X timed out. When enabled, and IORDY monitoring bit is also enabled, during
Channel X PIO operation, the watchdog counter starts counting when IORDY signal is deasserted. If after
256 PCI clocks, the IORDY signal is still deasserted, the Watchdog Timer expires, this bit is set, the
SiI3114 continues its operation, and stops monitoring IORDY signal. Software writes one to clear this bit.
Once this bit is cleared, the SiI3114 starts monitoring IORDY on channel X again.
on Channel X . This bit provides real-time status of the Channel X interrupt.
Virtual DMA data transfer has completed. This bit is cleared when PBM enable (bit 0 in PCI Bus Master –
Channel X ) is cleared.
Command is currently active. This bit is set when the first command byte is written to the command buffer.
This bit is cleared when all of the task file bytes, including the command byte, have been written to the
device.
to set the data transfer mode during PCI DMA transfer: 00
transfer.
to set the data transfer mode during PCI DMA transfer: 00
transfer.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
H
/ F4
H
/ 2B4
H
/ 2F4
H
Reserved
66
B
B
or 01
or 01
B
B
= PIO transfer; 10
= PIO transfer; 10
B
B
or 11
or 11
© 2007 Silicon Image, Inc.
Silicon Image, Inc.
B
B
= DMA
= DMA