74LVC3G14GT,115 NXP Semiconductors, 74LVC3G14GT,115 Datasheet

IC TRPL INV SCHMITT TRIG 8-XSON

74LVC3G14GT,115

Manufacturer Part Number
74LVC3G14GT,115
Description
IC TRPL INV SCHMITT TRIG 8-XSON
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet

Specifications of 74LVC3G14GT,115

Number Of Circuits
3
Logic Type
Inverter with Schmitt Trigger
Package / Case
8-XSON
Number Of Inputs
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
1.65 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
High Level Output Current
- 32 mA
Low Level Output Current
32 mA
Propagation Delay Time
3.8 ns, 3.2 ns , 2.4 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC3G14GT-G
74LVC3G14GT-G
935278934115
1. General description
2. Features and benefits
3. Applications
The 74LVC3G14 provides three inverting buffers with Schmitt trigger action.
The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of
this device in a mixed 3.3 V and 5 V environment. Schmitt trigger action at the inputs
makes the circuit tolerant of slower input rise and fall time. This device is fully specified for
partial power-down applications using I
preventing the damaging backflow current through the device when it is powered down.
74LVC3G14
Triple inverting Schmitt trigger with 5 V tolerant input
Rev. 8 — 19 August 2010
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
ESD protection:
±24 mA output drive (V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Unlimited rise and fall times
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C.
Wave and pulse shaper for highly noisy environment
Astable multivibrator
Monostable multivibrator.
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
OFF
. The I
OFF
circuitry disables the output,
Product data sheet

Related parts for 74LVC3G14GT,115

74LVC3G14GT,115 Summary of contents

Page 1

Triple inverting Schmitt trigger with 5 V tolerant input Rev. 8 — 19 August 2010 1. General description The 74LVC3G14 provides three inverting buffers with Schmitt trigger action. The inputs can be driven from either 3 ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74LVC3G14DP −40 °C to +125 °C 74LVC3G14DC −40 °C to +125 °C 74LVC3G14GT −40 °C to +125 °C 74LVC3G14GF −40 °C to +125 °C 74LVC3G14GD 74LVC3G14GM −40 °C to +125 °C − ...

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... NXP Semiconductors 6. Functional diagram 001aah728 Fig 1. Logic symbol 7. Pinning information 7.1 Pinning 74LVC3G14 GND 001aag081 Fig 4. Pin configuration SOT505-2 and SOT765-1 74LVC3G14 Product data sheet Triple inverting Schmitt trigger with 5 V tolerant input 001aah729 Fig 2. IEC logic symbol Fig 5. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 All information provided in this document is subject to legal disclaimers ...

Page 4

... NXP Semiconductors 74LVC3G14 GND 4 Transparent top view Fig 6. Pin configuration SOT996-2 7.2 Pin description Table 3. Pin description Symbol Pin SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 1A, 2A 1Y, 2Y GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level ...

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... NXP Semiconductors 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

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... NXP Semiconductors 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF I supply current CC Δ ...

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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage current OFF I supply current CC ΔI additional supply current CC [1] All typical values are measured at maximum V Table 8. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see ...

Page 8

... NXP Semiconductors 12. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay nA to nY; see power dissipation capacitance [1] Typical values are measured the same as t and PLH PHL [ used to determine the dynamic power dissipation (P PD × ...

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... NXP Semiconductors Table 10. Measurement points 1. 2.7 V 2 3 5.5 V Test data is given in Table R = Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 9 ...

Page 10

... NXP Semiconductors Fig 12. Typical transfer characteristics 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula add P = additional power dissipation (μW); add f = input frequency (MHz input rise time (ns input fall time (ns ...

Page 11

... NXP Semiconductors Linear change of V between 0 2.0 V. All values given are typical unless otherwise specified. I (1) Positive-going edge. (2) Negative-going edge. Fig 13. Δ function of V CC(AV ≈ --------------------- f = × T 0.8 RC Fig 14. Relaxation oscillator 74LVC3G14 Product data sheet Triple inverting Schmitt trigger with 5 V tolerant input 50 Δ ...

Page 12

... NXP Semiconductors 16. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.00 0.75 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 14

... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 15

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 16

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 19. Package outline SOT996-2 (XSON8U) ...

Page 17

... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

Page 18

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.2 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.25 mm nom 0.15 1.20 min 0.12 1.15 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 19

... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1.35 x 1 (2) (8×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 20

... NXP Semiconductors 17. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic UTLP Ultra-Thin Leadless Package 18. Revision history Table 13. Revision history Document ID Release date 74LVC3G14 v.8 20100819 • ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 22

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 20. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVC3G14 Product data sheet Triple inverting Schmitt trigger with 5 V tolerant input 19 ...

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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 4 9 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 13 Waveforms ...

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