LTC1400 LINER [Linear Technology], LTC1400 Datasheet - Page 13

• Manufacturer Part Number: LTC1400
• Description: Complete SO-8, 12-Bit, 400ksps ADC with Shutdown
• Manufacturer: LINER [Linear Technology]

APPLICATIONS
350ns. In the Sleep mode, power consumption is reduced
to a minimum by cutting off the supply to all internal
circuitry including the reference. Figure 12 shows the
ways to power down the LTC1400. The chip can enter the
Nap mode by keeping the CLK signal low and pulsing the
CONV signal twice. For Sleep mode operation, CONV
signal should be activated four times while CLK is kept low.
The LTC1400 can be returned to active mode easily. The
rising edge of CLK will wake-up the LTC1400. During the
transition from Sleep mode to active mode, the V
voltage ramp-up time is a function of the loading condi-
tions. With a 10 F bypass capacitor, the wake-up time
from Sleep mode is typically 4ms. A REFRDY signal will be
activated once the reference has settled and is ready for an
A/D conversion. This REFRDY bit is output to the D
before the rest of the A/D converted code.
S/H STATUS
INTERNAL
CONV
D
CLK
OUT
CLK
D
OUT
SAMPLE
U
INFORMATION
U
1
Hi-Z
t
3
t
t
t
10
2
6
2
t
REFRDY D11
4
t
8
W
3
V
IH
4
Figure 13. ADC Digital Timing Diagram
D10
Figure 14. CLK to D
5
U
D9
OUT
V
V
OH
OL
6
D8
REF
pin
HOLD
t
SAMPLE
7
t
CONV
D7
DIGITAL INTERFACE
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the D
the conversion result in serial form.
Figure 13 shows the digital timing diagram of the LTC1400
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
to CLK rising edge is less than t
delayed by one clock cycle.
The digital output data is updated on the rising edge of the
CLK line. D
system on the rising CLK edge. Data remains valid for a
minimum time of t
capture to occur.
8
CLK
D
OUT
D6
OUT
9
Delay
D5
10
OUT
D4
11
data should be captured by the receiving
D3
t
10
9
12
t
5
after the rising CLK edge to allow
D2
13
D1
V
IH
14
SAMPLE
2,
t
7
t
D0
ACQ
the digital output will be
t
15
8
LTC1400 • F14
OUT
90%
10%
Hi-Z
1
output provides
LTC1400
2
REFRDY
HOLD
LTC1400 • F13
13