SC16C650BIBS PHILIPS [NXP Semiconductors], SC16C650BIBS Datasheet - Page 11

• Manufacturer Part Number: SC16C650BIBS
• Description: 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9397 750 14451
Product data
6.1 Internal registers
6.2 FIFO operation
The SC16C650B provides 17 internal registers for monitoring and control. These
registers are shown in
in the standard 16C550. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C550
features and capabilities, the SC16C650B offers an enhanced feature register set
(EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control. Register
functions are more fully described in the following paragraphs.
Table 3:
[1]
[2]
[3]
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The SC16C650B provides independent trigger
levels for both receiver and transmitter. To remain compatible with SC16C550, the
transmit interrupt trigger level is set to 16 following a reset. It should be noted that the
user can set the transmit trigger levels by writing to the FCR register, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Enhanced register set (EFR, Xon/off 1-2)
0
1
1
1
1
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to “BF”
(HEX).
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
Internal registers decoding
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
Rev. 03 — 10 December 2004
READ mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Table
3. Twelve registers are similar to those already available
UART with 32-byte FIFOs and IrDA encoder/decoder
[2]
[3]
WRITE mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SC16C650B
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