AD7476ART Analog Devices, AD7476ART Datasheet - Page 12

• Manufacturer Part Number: AD7476ART
• Description: 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23
• Manufacturer: Analog Devices

AD7476/AD7477/AD7478
required to complete the conversion and access the complete
conversion result. CS may idle high until the next conversion or
may idle low until CS returns high sometime prior to the next
conversion, (effectively idling CS low).
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be per-
formed at a high throughput rate and the ADC is then powered
down for a relatively long duration between these bursts of sev-
eral conversions. When the AD7476/AD7477/AD7478 is in
power-down, all analog circuitry is powered down.
To enter power-down, the conversion process must be interrupted
by bringing CS high anywhere after the second falling edge of
SCLK and before the 10th falling edge of SCLK as shown in
Figure 18. Once CS has been brought high in this window of
SCLKs, the part will enter power-down and the conversion that
was initiated by the falling edge of CS will be terminated and
SDATA will go back into three-state. If CS is brought high
before the second SCLK falling edge, the part will remain in
normal mode and will not power-down. This will avoid acciden-
tal power-down due to glitches on the CS line.
In order to exit this mode of operation and power the AD7476/
AD7477/AD7478 up again, a dummy conversion is performed.
On the falling edge of CS the device will begin to power up, and
will continue to power up as long as CS is held low until after
the falling edge of the 10th SCLK. The device will be fully pow-
ered up once 16 SCLKs have elapsed and, as shown in Figure
19, valid data will result from the next conversion. If CS is brought
high before the 10th falling edge of SCLK, the AD7476/AD7477/
AD7478 will again go back into power-down. This avoids
accidental power-up due to glitches on the CS line or an inadvertent
burst of eight SCLK cycles while CS is low. So although the
device may begin to power up on the falling edge of CS, it will
again power down on the rising edge of CS as long as it occurs
before the 10th SCLK falling edge.
Power-Up Time
The power-up time of the AD7476/AD7477/AD7478 is typi-
cally 1 µs, which means that with any frequency of SCLK up to
20 MHz, one dummy cycle will always be sufficient to allow the
device to power-up. Once the dummy cycle is complete, the ADC
will be fully powered up and the input signal will be acquired
properly. The quiet time t
QUIET
SDATA
SCLK
, has elapsed by again bringing CS low.
CS
A
1
THE PART BEGINS
TO POWER UP
QUIET
must still be allowed from the
INVALID DATA
10
16
point at which the bus goes back into three-state after the dummy
conversion, to the next falling edge of CS. When running at 1 MSPS
throughput rate, the AD7476/AD7477/AD7478 will power up and
acquire a signal within ± 0.5 LSB in one dummy cycle, i.e., 1 µs.
When powering up from the power-down mode with a dummy
cycle, as in Figure 19, the track and hold that was in hold mode
while the part was powered down, returns to track mode after
the first SCLK edge the part receives after the falling edge of
CS. This is shown as Point A in Figure 19. Although at any SCLK
frequency one dummy cycle is sufficient to power up the device
and acquire V
cycle of 16 SCLKs must always elapse to power up the device
and fully acquire V
device and acquire the input signal. If, for example, a 5 MHz
SCLK frequency were applied to the ADC, the cycle time would
be 3.2 µs. In one dummy cycle, 3.2 µs, the part would be powered
up and V
SCLK only five SCLK cycles would have elapsed. At this stage,
the ADC would be fully powered up and the signal acquired. So,
in this case, the CS can be brought high after the 10th SCLK fall-
ing edge and brought low again after a time t
conversion.
When power supplies are first applied to the AD7476/AD7477/
AD7478, the ADC may power up in either power-down mode
or in normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure the part is fully powered up before
attempting a valid conversion. Likewise, if it is intended to keep
the part in the power-down mode while not in use and the user
wishes the part to power up in power-down mode, the dummy
cycle may be used to ensure the device is in power-down by ex-
ecuting a cycle such as that shown in Figure 18. Once supplies are
applied to the AD7476/AD7477/AD7478, the power-up time is
the same as that when powering up from the power-down mode.
It takes approximately 1 µs to fully power up if the part powers
up in normal mode. It is not necessary to wait 1 µs before execut-
ing a dummy cycle to ensure the desired mode of operation.
Instead, the dummy cycle can occur directly after power is
supplied to the ADC. If the first valid conversion is then per-
formed directly after the dummy conversion, care must be taken
to ensure that adequate acquisition time has been allowed. As
mentioned earlier, when powering up from the power-down
mode, the part will return to track upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
powers up initially after supplies are applied, the track and hold
will already be in track. This means that if the ADC powers up
in the desired mode of operation, and a dummy cycle is not re-
quired to change mode, a dummy cycle is not required to place
the track and hold into track.
1
IN
THE PART IS FULLY POWERED
UP WITH V
fully acquired. However after 1 µs with a 5 MHz
IN
, it does not necessarily mean that a full dummy
IN
IN
FULLY ACQUIRED
; 1 µs will be sufficient to power up the
VALID DATA
QUIET
16
to initiate the