AD7476ART Analog Devices, AD7476ART Datasheet - Page 9

• Manufacturer Part Number: AD7476ART
• Description: 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23
• Manufacturer: Analog Devices

CIRCUIT INFORMATION
The AD7476/AD7477/AD7478 are, respectively, fast, micro-
power, 12-bit, 10-bit, and 8-bit, single supply, A/D converters.
The parts can be operated from a 2.35 V to 5.25 V supply.
When operated from either a 5 V supply or a 3 V supply, the
AD7476/AD7477/AD7478 are capable of throughput rates of
1 MSPS when provided with a 20 MHz clock.
The AD7476/AD7477/AD7478 provide the user with an on-chip
track/hold, A/D converter, and a serial interface housed in a tiny
6-lead SOT-23 package, which offers the user considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the part and also provides the
clock source for the successive-approximation A/D converter. The
analog input range is 0 to V
required for the ADC, nor is there a reference on-chip. The ref-
erence for the AD7476/AD7477/AD7478 is derived from the
power supply and thus gives the widest dynamic input range.
The AD7476/AD7477/AD7478 also feature a power-down option
to save power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7476/AD7477/AD7478 is a successive-approximation ana-
log-to-digital converter based around a charge redistribution DAC.
Figures 8 and 9 show simplified schematics of the ADC. Figure 8
shows the ADC during its acquisition phase. SW2 is closed and
SW1 is in position A, the comparator is held in a balanced condi-
tion, and the sampling capacitor acquires the signal on V
When the ADC starts a conversion (see Figure 9), SW2 will open
and SW1 will move to Position B causing the comparator to
become unbalanced. The Control Logic and the Charge Redistri-
bution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figures 10 and 11 show the ADC transfer function.
V
V
IN
IN
SW1
SW1
AGND
AGND
A
B
A
B
CONVERSION
ACQUISITION
CAPACITOR
CAPACITOR
SAMPLING
SAMPLING
PHASE
V
V
PHASE
DD
DD
/2
/2
DD
SW2
SW2
. An external reference is not
COMPARATOR
COMPARATOR
REDISTRIBUTION
REDISTRIBUTION
CHARGE
CHARGE
CONTROL
CONTROL
DAC
DAC
LOGIC
LOGIC
IN
.
ADC TRANSFER FUNCTION
The output coding of the AD7476/AD7477/AD7478 is straight
binary. For the AD7476/AD7477, designed code transitions
occur midway between successive integer LSB values (i.e.,
1/2 LSB, 3/2 LSBs, etc.). The LSB size for the AD7476 is =
V
ideal transfer characteristic for the AD7476/AD7477 is shown
in Figure 10.
For the AD7478, designed code transitions occur midway be-
tween successive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.).
The LSB size for the AD7478 is V
characteristic for the AD7478 is shown in Figure 11.
TYPICAL CONNECTION DIAGRAM
Figure 12 shows a typical connection diagram for the AD7476/
AD7477/AD7478. V
such V
input range of 0 V to V
16-bit word with four leading zeros followed by the MSB of the
12-bit, 10-bit, or 8-bit result. The 10-bit result from the AD7477
will be followed by two trailing zeros. The 8-bit result from
the AD7478 will be followed by four trailing zeros.
DD
/4096 and the LSB size for the AD7477 is = V
111 ... 111
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
111 ... 111
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
DD
should be well decoupled. This provides an analog
0V
0V
1LSB
0.5LSB
AD7476/AD7477/AD7478
REF
DD
is taken internally from V
. The conversion result is output in a
ANALOG INPUT
ANALOG INPUT
DD
1LSB = V
/256. The ideal transfer
1LSB = V
1LSB = V
DD
DD
DD
V
V
/256 (AD7478)
DD
/4096 (AD7476)
/1024 (AD7477)
DD
–1LSB
–1.5LSB
DD
DD
/1024. The
and as