SAA7113 Philips Semiconductors, SAA7113 Datasheet - Page 56

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SAA7113

Manufacturer Part Number
SAA7113
Description
9-bit video input processor
Manufacturer
Philips Semiconductors
Datasheet

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Philips Semiconductors
15.2.9
Table 35 Sync control SA 08, D7 to D5, D3 to D0
1999 Jul 01
Vertical noise reduction (VNOI)
Normal mode (recommended setting)
Fast mode [applicable for stable sources only;
automatic field detection (AUFD) must be disabled]
Free running mode
Vertical noise reduction bypassed
Horizontal PLL (HPLL)
PLL closed
PLL open; horizontal frequency fixed
Horizontal time constant selection (HTC1 and HTC0)
TV mode (recommended for poor quality TV signals
only; do not use for new applications)
VTR mode (recommended if a deflection control circuit
is directly connected to SAA7113H)
Reserved
Fast locking mode (recommended setting)
Forced ODD/EVEN toggle FOET
ODD/EVEN signal toggles only with interlaced source
ODD/EVEN signal toggles fieldwise even if source is
non-interlaced
Field selection (FSEL)
50 Hz, 625 lines
60 Hz, 525 lines
Automatic field detection (AUFD)
Field state directly controlled via FSEL
Automatic field detection
9-bit video input processor
S
UBADDRESS
08H
FUNCTION
56
HTC1 and HTC0
HTC1 and HTC0
HTC1 and HTC0
HTC1 and HTC0
CONTROL BIT
VNOI1
VNOI0
VNOI1
VNOI0
VNOI1
VNOI0
VNOI1
VNOI0
AUFD
AUFD
FOET
FOET
HPLL
HPLL
FSEL
FSEL
LOGIC LEVEL
00
01
10
11
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
Product specification
SAA7113H
D4 and D3
D4 and D3
D4 and D3
D4 and D3
DATA BIT
D1
D0
D1
D0
D1
D0
D1
D0
D2
D2
D5
D5
D6
D6
D7
D7

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