CS49300 Cirrus Logic, CS49300 Datasheet

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... Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com CS49300 Family DSP Description The CS493XX is a family of multichannel audio decoders intended to supersede the CS4923/4/5/6/7/8/9 family as the leader of audio decoding in both the DVD, broadcast and receiver markets ...

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... AT&T, the Fraunhofer Institute, Dolby Laboratories, and the Sony Corporation. In regards to the MP3 capable functionality of the CS49300 Family DSP (via downloading of mp3_493xxx_vv.ld and mp3e_493xxx_vv.ld application codes) the following statements are applicable: “Supply of this product conveys a license for personal, private and non-commercial use. ...

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... Parallel Delivery with Parallel Control ........................................................ 69 10.4.2 Parallel Delivery with Serial Control ........................................................... 70 10.5 Digital Audio Output Port ......................................................................................... 70 10.5.1 IEC60958 Output ........................................................................................ 71 11.HARDWARE CONFIGURATION ................................................................................... 72 11.1 Address Checking ................................................................................................... 72 11.2 Input Data Hardware Configuration ........................................................................ 72 11.2.1 Input Configuration Considerations ......................................................... 75 11.3 Output Data Hardware Configuration ...................................................................... 76 11.3.1 Output Configuration Considerations ........................................................ 78 11.4 Creating Hardware Configuration Messages .......................................................... 78 DS339PP4 CS49300 Family DSP 3 ...

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... Figure 31. External Memory Read (16-bit address) ......................................................................... 51 Figure 32. External Memory Write (16-bit address) .......................................................................... 51 Figure 33. Typical Serial Boot and Download Procedure ................................................................. 53 Figure 34. Typical Parallel Boot and Download Procedure .............................................................. 54 Figure 35. Autoboot Timing Diagram ................................................................................................ 56 Figure 37. Autoboot INTREQ Behavior ............................................................................................ 57 Figure 36. Autoboot Sequence ......................................................................................................... 58 4 CS49300 Family DSP DS339PP4 ...

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... A)..................................................................................................................................... 76 Table 23. Output Data Format Configuration (Parameter B)..................................................................................................................................... 76 Table 24. Output MCLK Configuration (Parameter C) .................................................................................................................................... 77 Table 25. Output SCLK Configuration (Parameter D) .................................................................................................................................... 77 Table 26. Output SCLK Polarity Configuration (Parameter E)..................................................................................................................................... 77 Table 27. Example Values to be Sent to CS493XX After Download or Soft Reset ........................... 79 DS339PP4 CS49300 Family DSP 5 ...

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... VA ||VA| – |VD IND T stg Symbol Positive digital VD Positive analog VA ||VA| – |VD Symbol Symbol Digital operating: VD[3:1] Analog operating: VA CS49300 Family DSP Min Max –0.3 2.75 –0.3 2.75 - 0.3 ±10 - –0.3 3.63 –65 150 Min Typ Max 2.37 2.5 2.63 2.37 2 Min ...

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... T rstsu T rsthld ins T T rst2z T rstl Figure 1. RESET Timing Symbol T clki T clkih T clkil T T clkih clkil T clki CS49300 Family DSP = 20 pF) L Min Max 100 - 530 - - rstsu rsthld = 20 pF) L Min Max 35 3800 18 18 Unit µ ...

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... DCLK for the particular application. 2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for characterization to minimize the effects of external bus capacitance. 3. See T from Intel Host Mode in idd 8 CS49300 Family DSP ® Host Mode Symbol T ias T ...

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... DS339PP4 idhr T idd T idis T T irpw ird ® Figure 3. Intel Parallel Host Mode Read Cycle ® Figure 4. Intel Parallel Host Mode Write Cycle CS49300 Family DSP T irdtw T iw trd 9 ...

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... DCLK for the particular application. 2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for characterization to minimize the effects of external bus capacitance. 3. See T from Motorola Host Mode in mdd 10 CS49300 Family DSP ® Host Mode = 20 pF) L Symbol Min ...

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... ® Parallel Host Mode Read Cycle cdw ® Parallel Host Mode Write Cycle CS49300 Family DSP hld trd 11 ...

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... This time is by design and not tested. 12 (Note 1) (Note 7) (Note 7) (Note 2) (Note 3) (Note 4) (Note 4) (Note 5, 7) (Note 7) indicates the maximum speed of the hardware. The system designer should be CS49300 Family DSP = 20 pF) L Symbol Min Max Units f - 2000 kHz sck t ...

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... DS339PP4 CS49300 Family DSP 13 ...

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... R/W bit (set to 1 for a read). This time is by design and is not tested. 6. With a 4.7k Ohm pull-up resistor this value is typically 215ns. As this pin is open drain adjusting the pull up value will affect the rise time. 7. This time is by design and not tested. 14 CS49300 Family DSP 2 ® C Control Port ...

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... DS339PP4 CS49300 Family DSP 15 ...

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... SCLKN1(2) is the point at which the data is valid. 4. This timing parameter is defined from the active edge of SCLKN1(2). The active edge of SCLKN1(2) is the point at which the data is valid. 5. Slave mode is defined as SCLKN1(2) and LRCLKN1(2) being driven by an external source. 16 CS49300 Family DSP = 20 pF) L Symbol Min ...

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... Figure 9. Digital Audio Input Data, Master and Slave Clock Timing DS339PP4 CS49300 Family DSP lrds T sc lki T T ...

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... Symbol T cmpclk T cmpsu T cmphld clk Figure 10. Serial Compressed Data Timing Symbol T cmpclk T cmpsu T cmphld psu cm phld T cm pclk CS49300 Family DSP = 20 pF) L Min Max - hld = 20 pF) L Min Max 4*DCLK + DS339PP4 Unit MHz ns ns ...

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... This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the point at which the data is valid. 5. Slave mode is defined as SCLK and LRCLK being driven by an external source. 6. This specification is characterized, not production tested. DS339PP4 CS49300 Family DSP = 20 pF) L Symbol Min ...

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... Figure 12. Digital Audio Output Data, Input and Output Clock Timing 20 T sdmi sclk T lrds sclk T lrts T stlr adss CS49300 Family DSP T mclk T mclk DS339PP4 ...

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... Decoder and PCM Upsampler) ™ ™ (MLP )* (for ES Please refer to the CS4932x/CS49330 Part Matrix vs. Code Matrix (PDF) document available from the CS49300 Web Site Page for the latest listing of audio decoding/processing algorithms. The part CS49300 Family DSP ™ ™ (AC-3 ) with ™ ...

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... PES layer decode for audio/video synchronization and DVD Audio Pack layer support. The CS49300 will support all of the above decoding and PCM processing standards. CS4931X - Broadcast Sub-family. The CS4931X sub-family is targeted at audio decoding in the broadcast markets in systems such as digital TV, HDTV, set-top boxes and digital audio broadcast units (digital radios) ...

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... CS493XX if the description applies to the entire CS49300 Family DSP description only applies to a particular sub-family, CS49300, CS4931X, CS4932X or CS49330 will be used. When CS49300, CS4931X, CS4932X or CS49330 is used, this should be interpreted as applying to all parts within the particular sub-family or a particular device ...

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... The CS493XX family of digital signal processors (DSPs) incorporate a large amount of flexibility into a 44 pin package. Because of the high degree 24 CS49300 Family DSP of integration, many of these pins are internally multiplexed to serve multiple purposes. Some pins are designed to operate in one mode at power up, and serve a different purpose when the DSP is running ...

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... Care should be taken when laying out the filter circuitry to minimize trace lengths and to avoid any close routing of high frequency signals. Any noise coupled on to the DS339PP4 CS49300 Family DSP filter circuit will be directly coupled into the PLL, which could affect performance. Reference Designator C1 ...

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... GPIO6 10 GPIO5 11 GPIO4 14 GPIO3 15 GPIO2 16 GPIO1 17 GPIO0 [8:0] 2 ® Figure 13 Control CS49300 Family DSP +2.5VA + + DAC ( ...

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... EMAD[7:0] 2 ® Figure 14 Control with External Memory CS49300 Family DSP +2.5VA FERRITE BEAD + + LRCLK 41 ...

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... GPIO8 8 GPIO7 9 GPIO6 10 GPIO5 11 GPIO4 14 GPIO3 15 GPIO2 16 GPIO1 17 GPIO0 Figure 15. SPI Control CS49300 Family DSP +2.5VA + 0 ...

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... :0] Figure 16. SPI Control with External Memory CS49300 Family DSP +2.5VA FERRITE BEAD + + ...

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... ® Figure 17. Intel Parallel Control Mode CS49300 Family DSP +2.5VA + 0 ...

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... ® Figure 18. Motorola Parallel Control Mode CS49300 Family DSP +2.5VA + ...

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... CLKIN pin is connected to 27 MHz. In other scenarios such as an A/V receiver design, the PLL can be clocked through the CLKIN pin with 32 CS49300 Family DSP even multiples of the desired sampling rate or with an already available clock source. Typically a 12.288 MHz CLKIN is used in this scenario so that the same oscillator can be used for the DSP and ADC ...

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... When all of the bytes have been transferred, chip select should be raised to signify an end of CS49300 Family DSP SPI START: CS (LOW) WRITE ADDRESS BYTE WITH MODE BIT SET TO 0 FOR WRITE ...

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... The 0x01 byte represents the 7 bit address 0000000b, and the least significant bit set designate a read. 4) After the falling edge of the serial control clock 34 CS49300 Family DSP INTREQ LOW? YES CS (LOW) WRITE ADDRESS BYTE ...

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... CS493XX to accept the write. In other words a byte of 0x00 should be clocked into the device preceding any write. The 0x00 byte represents the 7 bit of address (0000000b) and the read/write bit set designate a write. CS49300 Family DSP Pin Name Pin Number SCCLK 7 SCDIO ...

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... CS49300 Family DSP DS339PP4 ...

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... After the falling edge of the serial control clock (SCCLK) for the read/write bit of the address byte, an acknowledge must be read in by the host. The CS493XX will drive SCDIO low to acknowledge the address byte and to indicate that it is ready for a read operation CS49300 Family DSP 2 ® ® ...

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... In other words, all data should be read out of the chip until INTREQ signals the last byte by going high as described above. Please see Section 6.1.3, “INTREQ Behavior: A Special Case” on page 39 INTREQ behavior. CS49300 Family DSP 2 ® C stop condition (SCDIO ® ...

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... The host is reading from the CS493XX when the unsolicited message is queued, but INTREQ goes DS339PP4 CS49300 Family DSP high for one period of SCCLK and then goes low again before the end of the read cycle. In case (1) the host should perform a read operation as discussed in the previous sections ...

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... CS49300 Family DSP DS339PP4 ...

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... Thus, the host should know how many bytes to expect based on the first byte (the OPCODE DS339PP4 CS49300 Family DSP read response message guaranteed that no read responses will begin with 0x00, which means that a NULL byte (0x00) detected in the OPCODE position of a read response message should be discarded. Please see an Application Code User’ ...

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... The host writes compressed data to the DSP input buffer at this address. (Write only HOSTMSG4 HOSTMSG3 MFC MFB PCMDATA4 PCMDATA3 CMPDATA4 CMPDATA3 Table 5. Parallel Input/Output Registers CS49300 Family DSP 2 1 HOSTMSG2 HOSTMSG1 HOSTMSG0 2 1 HINBSY HOUTRDY Reserved 2 1 PCMDATA2 PCMDATA1 PCMDATA0 2 1 CMPDATA2 CMPDATA1 CMPDATA0 DS339PP4 0 ...

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... Motorola and Intel sections. The following will be covered: DS339PP4 CS49300 Family DSP • Flow diagram and description for a control write • ...

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... Once the data is valid, the host can read the value of the selected register from the DATA[7:0] pins of the CS493XX. ADDRESS A PARALLEL I/O REGISTER (A[1:0] SET APPROPRIATELY READ BYTE FROM Figure 25. Intel Mode, One-Byte Read Flow Diagram CS49300 Family DSP Figure 25 illustrates Figure 25 A[1:0]==00b. A[1:0]==01b ( ...

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... Once the setup time for the write has been met ADDRESS A PARALLEL I/O REGISTER 7 (A[1:0] SET APPROPRIATELY Figure 26. Motorola Mode, One-Byte Write Flow CS49300 Family DSP Figure 26 illustrates A[1:0]==00b. A[1:0]==01b. A[1:0]==10b. A[1:0]==11b. R/W (LOW ( WRITE BYTE TO DATA [7:0] CS (HIGH) DS (HIGH) Diagram 45 ...

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... In order to determine whether the CS493XX is ready to accept a new control byte the host must check the HINBSY bit of the Host Control Register (bit 2). If HINBSY is high, then the DSP is not prepared to accept a new control CS49300 Family DSP or Write_Byte_INT(). Figure 28 will now be ...

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... TO WRITE? NO FINISHED Figure 28. Typical Parallel Host Mode Control Write Sequence Flow Diagram DS339PP4 CS49300 Family DSP byte response from the DSP. The host must read the response byte and act accordingly. The boot procedure is discussed in on page 52. During regular operation (at run-time), the responses from the CS493XX will always be 6 bytes in length ...

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... CS493XX. EMAD[7:0] serve as a multiplexed address and data bus. EMOE is an active-low external-memory data output enable as well as the address latch strobe. EMWR is an active low write enable. CS49300 Family DSP 2 C, the DS339PP4 ...

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... Sometimes it is desirable for the external memory to be paged by the host controller. One application where this is useful is the autoboot mechanism (discussed in Section 8.2, “Autoboot” on page Using paged memory allows multiple dsp firmware applications to be stored in the same memory, with CS49300 Family DSP 32 for details). 56). 49 ...

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... The host controller should directly control all address bits outside of the memory space to be used by the DSP CS49300 Family DSP kilobyte pages are desired to hold each application code, the DSP would need 15 bits for the address space. The system designer would connect the 15 ...

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... Please see section 2, Serial Communication for R2 R4 more details. Figure 30. External Memory Interface MA15:8 MA 23:16 MA15:8 MA 23:16 CS49300 Family DSP ADDR[7: A[7:0] ADDR[14:8] 32K MA7:0 Data7:0 ...

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... RD, and PSEL). Section 11, 2) The host should then send the boot message 72. DOWNLOAD_BOOT causes the CS493XX to initialize itself for download the initialization was successful the CS49300 Family DSP MNEMONIC VALUE SOFT_RESET 0x000001 RESERVED 0x000002 RESERVED 0x000003 ...

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... TIMEOUT AFTER 20MS (NOTE typical but this time is 5. Hardware configuration EXIT(ERROR) WRITE_*(SW_CONFIG_MSG, SW_MSG_SIZE) (NOTE 5) CS49300 Family DSP 500 µs WAIT t . rstl pins are used to configure the CS493XX serial communication mode. These mode pins are latched internally on the rising edge of reset ...

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... TIMEOUT AFTER 20MS (NOTE typical but this time is 5. Hardware configuration EXIT(ERROR) WRITE_*(SW_CONFIG_MSG, SW_MSG_SIZE) (NOTE 5) CS49300 Family DSP WRITE_*(DOWNLOAD_ 500 µs BOOT, MSG_SIZE rstl pins are used to configure the CS493XX serial communication mode. These mode pins are latched internally on the rising edge of reset ...

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... BOOT_SUCCESS_RECEIVED (0x000005) which will cause an internal application downloaded application to run. 8) After waiting 5ms to allow the downloaded application to initialize, the host can send configuration messages for both hardware and software configuration. CS49300 Family DSP (0x000004). the CS493XX will send with the BAD_CHECKSUM ...

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... ROM. Thus, the two latches catch the least significant bytes, and the most significant byte is dropped. Section 6. 23: 15:8 Figure 35. Autoboot Timing Diagram CS49300 Family DSP discusses the Figure 30, to the Figure 35, "Autoboot Timing there may appear 7:0 Data7:0 ...

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... DSP clock. The autoboot sequence is specified to complete within 200 ms rstsu Download in Progress T rsthld Figure 37. Autoboot INTREQ Behavior CS49300 Family DSP Section 11, 72. in Figure 37, "Autoboot 57, the host must drive ABOOT Driven Low by Host ...

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... Wait times should be verified by the designer. 4. The READ_* and WRITE_* functions are placeholders for the READ_I2C/READ_SPI and WRITE_I2C/WRITE_SPI functions defined in 6.1, “Serial Communication” on page Figure 36. Autoboot Sequence CS49300 Family DSP . rstl ) and hold rstsu Section 33. DS339PP4 ...

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... CS49300 Family DSP below in Table 11 using gfabt6.ld, and gfabt4.ld GFABT4.LD GFABT6.LD GFABT8.LD ac3_pl~1.ld ac3_pl~1.ld ac3_pl~1. ...

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... All actual Autoboot times should be verified by the designer. 6. The READ_* and WRITE_* functions are placeholders for the READ_I2C/READ_SPI and WRITE_I2C/WRITE_SPI functions defined in Communication” on page CS49300 Family DSP 500 µs WAIT TIMEOUT AFTER 20MS (NOTE 3) N EXIT(ERROR) ...

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... The IBA codes are typically around 350 bytes in size and hence can easily be stored in a host controller. DS339PP4 CS49300 Family DSP 8.5. Application Failure Boot Message Each piece of application code is specifically tailored for an individual part in the CS493XX family. Although it is possible to load a piece of ...

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... Configuration messages determine both hardware and software configuration. Hardware configurations are described in Section 11 application configuration messages are described in the Application Code User’s Guide for the code being used. Figure 39. Performing a Reset CS49300 Family DSP . rstl Section 6, “Control” this manual. Software DS339PP4 ...

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... The memory image given in Figure example of a non-paged memory image. Only 15 of the 16 output bits of the address latches would be connected to address bits A0-A14 of the CS49300 Family DSP IBA Code(s) Stored in Host Type of Design Dolby Digital with Dolby Digital with PL II, Pro Logic II 5 ...

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... INTREQ behavior (mask the INTREQ interrupt). The host can then verify that the code has successfully initialized itself by reading a variable from the application and 64 CS49300 Family DSP 0x00000 D olb y D igital with Pro Logic II with C irrus Ex tra S urround ...

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... CDB49300-MEMA.0 is made accessible by the DSP when the host drives uC18 high. The external 256 Kilobyte EPROM is accessible to the DSP when the host controller drives uC18 low. The with uC15, uC16, and uC17 lines are used to page between the various code images. CS49300 Family DSP 65 ...

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... CS49300 Family DSP DS339PP4 ...

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... The one data line with M bits per channel. Channels 0, 2, and 4 are presented while the LRCLK is high and channels are presented while the LRCLK is low. Data is valid on the rising edge of SCLK and CS49300 Family DSP Format" on page 68 shows the I ...

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... lock locks annel hann el Figure 45. Multichannel Format CS49300 Family DSP Pin Description Pin Number Serial Data In Secondary STC clock Serial Bit Clock Frame Clock Table 13. Digital Audio Input Port ...

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... If the MFB bit (CMPREQ) is high, no more data should be sent to the CS493XX. Once the MFB bit (CMPREQ) has gone low again, the host may send another block of compressed audio data. CS49300 Family DSP Section 6.2, 41, then Section 6.2, “ ...

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... LRCLK SCLK MCLK MCLK is the master clock and is firmware configurable to be either an input or an output. If MCLK used as an output, the internal PLL must be used output MCLK can be CS49300 Family DSP SPI control, bytewide delivery can still be achieved Pin Description ...

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... RS422 device or an optocoupler as its outputs are only CMOS. Please consult software user’s guide to determine if this pin is supported by the download code being used. CS49300 Family DSP shows the mapping of DAO channels to Subframe 0 Left AUDATA0 ...

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... The parameters are defined as follows Data Type Section 6. Data Format (This is a don’t care for parallel 33 necessary modes of data delivery) CS49300 Family DSP 1 = Address checking Address checking off 2 S, Left Justified, Parallel, or DS339PP4 ...

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... AC-3, DTS, MPEG Multichannel, AAC or MP3 elementary 0x003FC0 stream data from a DVD or IEC60958- 0x800110 packed elementary stream DTS data 0x0E002B from a DTS-CD) Table 19. Input Data Format Configuration CS49300 Family DSP Hex Data Type Message 0x800210 0x003FC0 0x800110 0x0E0023 0x800210 0x003FC0 ...

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... Multichannel PCM (4 Channel) 0x80021A - Left Justified 20-bit 0x8080FF (used only by special post-processing 0x800117 application codes) 0x0048C0 0x80011A 0x0018C0 Table 19. Input Data Format Configuration (Input Parameter B) (Continued) CS49300 Family DSP Hex Data Format Message 0x800217 0x8080FF 0x80021A 0x8080FF 0x800117 0x0018C0 0x80011A 0x0018C0 ...

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... PCM may now 0x000020 have a Robustness” which does alleviate the above problem, however you should still follow the above recommendation. CS49300 Family DSP Hex Message 0x800014 0x280D00 0x800014 0x820300 (Input Parameter formats. For compressed ...

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... AUDATA3 as S/PDIF (IEC60958) or Digital Audio in the format of I covered in AN162 and AN163) Table 23. Output Data Format Configuration CS49300 Family DSP Hex Message 0x80027F 0xFC7FFF 0x80027C 2 0xF01F00 S or Left Justified is 0x80027D ...

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... E Value 0x010000 0 Data Valid on Rising Edge 0x80027C (default) (clocked out on falling) 0xF01F00 1 Data Valid on Falling Edge (clocked out on rising) Table 26. Output SCLK Polarity Configuration CS49300 Family DSP Hex MCLK Frequency Message 0x80027F 0xFFE7FF 0x80027F 0xFFE7FF 0x80017F 0x001000 0x80027F 0xFFE7FF 0x80017F ...

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... DAO: Left Justified slave mode (LRCLK, SCLK inputs) MCLK @ 256Fs SCLK @ 64Fs The above configuration corresponds to OUTPUT which has a configuration message of: 0x80027F 0xFC7FFF 0x80027C 0xF01F00 0x80027D 0xF01F00 CS49300 Family DSP DS339PP4 ...

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... Table 27. Example Values to be Sent to CS493XX After Download or Soft Reset DS339PP4 VALUE 0x001800 0x80027F 0xFC7FFF 0x80027C 0xF01F00 0x80027D 0xF01F00 0x80027E 0xF01F00 0x80017F 0x018000 CS49300 Family DSP 79 ...

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... Top View CS49300 Family DSP MCLK SCLK LRCLK FILT1 FILT2 ...

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... Motorola parallel host mode, this pin serves as the active-low data-strobe-input signal. In serial host mode, this pin can serve as the external-memory active-low write-enable output signal. Also in serial host mode, this pin can serve as a general purpose input or output bit. BIDIRECTIONAL - Default: INPUT DS339PP4 CS49300 Family DSP 2 C clock input. INPUT 81 ...

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... DGND as output until enabled by the DSP software. OUTPUT AUDATA0—Digital Audio Output 0: Pin 41 PCM multi-format digital-audio data output, capable of two-, four-, or six-channel 20-bit output. This PCM output defaults to DGND as output until enabled by the DSP software. OUTPUT 82 CS49300 Family DSP DS339PP4 ...

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... CS493XX clocks. In master mode, LRCLKN1 is derived from the CS493XX internal clock generator. In either master or slave mode, the polarity of LRCLKN1 for a particular subframe can be programmed by the DSP. BIDIRECTIONAL - Default: INPUT DS339PP4 CS49300 Family DSP Left Justified 83 ...

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... When in this mode, the CS493XX internal PLL is driven by the clock recovered from the incoming data stream. INPUT DC—Reserved: Pin 38 This pin is reserved and should be pulled up with an external 4.7k resistor. DD—Reserved: Pin 37 This pin is reserved and should be pulled up with an external 4.7k resistor. 84 CS49300 Family DSP DS339PP4 ...

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... Temp Range 0-70º C Temp Range 0-70º C Temp Range -40-85º INCHES MAX 0.180 0.120 0.021 0.695 0.656 0.630 0.695 0.656 0.630 0.060 CS49300 Family DSP e D2/ MILLIMETERS MIN MAX 4.191 4.572 2.286 3.048 .330 0.533 17.399 17.653 16.510 16.662 14 ...

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