CS49300 Cirrus Logic, CS49300 Datasheet - Page 19

• Manufacturer Part Number: CS49300
• Description: Multi-Standard Audio Decoder Family
• Manufacturer: Cirrus Logic

1.14. Switching Characteristics — Digital Audio Output
(T
Notes: 1. MCLK can be an input or an output. These specifications apply for both cases.
DS339PP4
MCLK period
MCLK duty cycle
SCLK period for Master or Slave mode
SCLK duty cycle for Master or Slave mode
Master Mode
SCLK delay from MCLK rising edge, MCLK as an input
SCLK delay from MCLK rising edge, MCLK as an output
LRCLK delay from SCLK transition
AUDATA2–0 delay from SCLK transition
Slave Mode
Time from active edge of SCLKN1(2) to LRCLKN1(2) transition
Time from LRCLKN1(2) transition to SCLKN1(2) active edge
AUDATA2–0 delay from SCLK transition
A
= 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
2. Master mode timing specifications are characterized, not production tested.
3. Master mode is defined as the CS493XX driving both SCLK and LRCLK. When MCLK is an input, it is
4. This timing parameter is defined from the non-active edge of SCLK. The active edge of SCLK is the
5. Slave mode is defined as SCLK and LRCLK being driven by an external source.
6. This specification is characterized, not production tested.
divided to produce SCLK and LRCLK.
point at which the data is valid.
Parameter
(Note 2, 3)
(Note 4, 6)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
(Note 4)
(Note 4)
(Note 5)
Symbol
T
T
T
T
T
T
T
T
T
sdmo
adsm
sdmi
adss
mclk
sclk
lrds
stlr
lrts
CS49300 Family DSP
L
= 20 pF)
Min
–5
40
40
40
45
10
10
Max
60
55
15
10
10
10
15
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
19