CS49300 Cirrus Logic, CS49300 Datasheet - Page 42

• Manufacturer Part Number: CS49300
• Description: Multi-Standard Audio Decoder Family
• Manufacturer: Cirrus Logic

42
Host Message (HOSTMSG) Register, A[1:0] = 00b
HOSTMSG7–0
Host Control (CONTROL) Register, A[1:0] = 01b
Reserved
CMPRST
PCMRST
MFC
MFB
HINBSY
HOUTRDY
Reserved
PCM Data Input (PCMDATA) Register, A[1:0] = 10b
PCMDATA7–0
Compressed Data Input (CMPDATA) Register, A[1:0] = 11b
CMPDATA7–0
HOSTMSG7
PCMDATA7
CMPDATA7
Reserved
7
7
7
7
HOSTMSG6
PCMDATA6
CMPDATA6
CMPRST
the internal DSP and the external host. This register typically passes multibyte messages car-
rying microcode, control, and configuration data. HOSTMSG is physically implemented as two
independent registers for input and output (read and write).
holds the port in reset. Writing zero enables the port. This bit must be low for normal operation.
(Write only)
port in reset. Writing zero enables the port. This bit must be low for normal operation. (Write
only)
register. The host reads this bit to determine if the last host byte written has been read by the
DSP. (Read only)
the HOSTMSG register. The DSP reads this bit to determine if the last DSP output byte has
been read by the host. (read only)
Host data to and from the DSP. A read or write of this register operates handshake bits between
Always write a 0 for future compatibility.
When set, initializes the CMPDATA compressed data input channel. Writing a one to this bit
When set, initializes the PCMDATA linear PCM input channel. Writing a one to this bit holds the
When high, indicates that the PCMDATA input buffer is almost full. (read only)
When high, indicates that the CMPDATA input buffer is almost full. (read only)
Set when the host writes to HOSTMSG. Cleared when the DSP reads data from the HOSTMSG
Set when the DSP writes to the HOSTMSG register. Cleared when the host reads data from
Always write a 0 for future compatibility.
The host writes PCM data to the DSP input buffer at this address. (Write only)
The host writes compressed data to the DSP input buffer at this address. (Write only)
6
6
6
6
HOSTMSG5
PCMDATA5
CMPDATA5
PCMRST
5
5
5
5
Table 5. Parallel Input/Output Registers
HOSTMSG4
PCMDATA4
CMPDATA4
MFC
4
4
4
4
HOSTMSG3
PCMDATA3
CMPDATA3
MFB
3
3
3
3
HOSTMSG2
PCMDATA2
CMPDATA2
HINBSY
CS49300 Family DSP
2
2
2
2
HOSTMSG1
PCMDATA1
CMPDATA1
HOUTRDY
1
1
1
1
HOSTMSG0
PCMDATA0
CMPDATA0
DS339PP4
Reserved
0
0
0
0