ADMC300-PB Analog Devices, ADMC300-PB Datasheet
ADMC300-PB
Related parts for ADMC300-PB
ADMC300-PB Summary of contents
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... DATA WATCH- PROGRAM DOG RAM RAM 1K 16 TIMER 4K 24 SERIAL PORTS INTERVAL AUXILIARY TIMER SPORT 0 SPORT Motor Controller ADMC300 PWMTRIP MOTOR CONTROL PERIPHERALS 3 2 PROGRAM EVENT ENCODER INTERRUPT CAPTURE INTERFACE CONTROLLER TIMERS PWM SIGMA-DELTA GENERATION PWM ADCs (Continued on Page 7) ...
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... ADMC300–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Digital Supply Voltage DD AV Analog Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter V Hi-Level Input Voltage IH V Lo-Level Input Voltage IL V Hi-Level Output Voltage OH V Lo-Level Output Voltage OL I Hi-Level Input Current IH Hi-Level PWMTRIP, PIO0–PIO11 Current ...
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... ADCDIVB = 0x180 10%, GND = AGND = AMB Test Conditions ( 10%, GND = AGND = otherwise noted) Test Conditions Double Update Mode 1 ADMC300 = 2. – +85 C, REFIN AMB Min Typ Max 72 76 –70 –82 – 2.5 V 10,600 ...
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... Specifications subject to change without notice. TIMING PARAMETERS Parameter Clock Signals t is defined as 0 The ADMC300 uses an input clock with a frequency equal CK CKI to half the instruction rate; a 12.5 MHz input clock (which is equivalent to 80 ns) yields processor cycle (equivalent to 25 MHz). t 0.5 t period should be substituted for all relevant timing parameters to obtain CKI specification value ...
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... Range ADMC300BST –40°C to +85°C ADMC300-ADVEVALKIT ADMC300-PB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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... I I/O PIO8 56 I I/O PIO9/CONVST 57 I I/O PIO10/ETU0 58 I I/O PIO11/ETU1 59 SUP GND AGND 60 GND PIN CONFIGURATION 80-Lead Plastic Thin Quad Flatpack (TQFP) (ST-80) ADMC300 TOP VIEW (Not to Scale) PIN 1 IDENTIFIER Pin Pin Pin Pin No. Type Name Name 61 GND GND GND GND V5N 63 I EIZP ...
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... ADMC300 integrates a 25 MIPS, fixed-point DSP core with a complete set of motor control peripherals that permits fast, efficient development of servo motor controllers. The DSP core of the ADMC300 is the ADSP-2171, which is completely code compatible with the ADSP-2100 DSP family and combines three computational units, data address genera- tors and a program sequencer ...
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... The sequencer supports conditional jumps and subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADMC300 executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. ...
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... Data Memory Data (DMD) Bus • Result (R) Bus Program memory can store both instructions and data, permit- ting the ADMC300 to fetch two operands in a single cycle— one from program memory and one from data memory. The ADMC300 can fetch an operand from on-chip program memory and the next instruction in the same cycle ...
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... IRQ2 interrupt. The programmable interrupt controller manages the masking and vector addressing of all eleven periph- eral interrupts. A detailed description of the operation of the entire interrupt system of the ADMC300 is given later, after a more detailed description of the various peripheral systems. Windows is a registered trademark of Microsoft Corporation. ...
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... SCLK1 RESET RFS1/ SROM Clock Signals The ADMC300 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified minimum frequency during normal operation external clock is used, it should be a TTL-compatible signal running at half the instruction rate ...
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... ADMC300, this register must always contain the value 0x8000 (which is the default). The configuration of both the SYSCNTL and MEMWAIT registers of the ADMC300 is shown at the end of the data sheet. ANALOG-TO-DIGITAL CONVERSION SYSTEM A functional block diagram of the ADC system of the ADMC300 is shown in Figure 5. The ADC system provides the high perfor- mance conversion required for precision applications ...
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... However, the ADMC300 also provides a reference output that could be buffered and used as a reference source for either or both banks. Input Configuration The input to each ADC may be applied to the ADMC300 in either a single-ended or differential configuration. In many cases, a single-ended configuration is easier to provide but the differential connection permits the reduction of common-mode noise from the input signal ...
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... AD580 is recommended. This reference is applied directly to both input reference pins, REFINA and REFINB, and is also applied to any external bias circuitry used to produce the ADC input signals. For a lower cost solution, the ADMC300 also provides a reference output that may be used to provide the V signal ...
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... The offset is defined by the ADCSYNC register as a fraction of the ADC update period in an identical manner to before. ADC Transfer Characteristics , Each ADC converter of the ADMC300 consists of an input OFFSET modulator stage and a decimation filter stage that produces the final conversion result. The output of the decimation filters are ...
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... ADC Interrupt Generation Two dedicated interrupts are associated with the ADC system of the ADMC300, one for each of the ADC banks. The inter- rupts are generated after the ADC data registers of the particu- lar bank have been updated by either an internal or external CONVST pulse ...
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... ADC Registers The composition of all the data registers associated with the ADC system of the ADMC300 is shown at the end of the data sheet. The reset values are shown for certain bits, where appropriate. THREE-PHASE PWM CONTROLLER The PWM generator block of the ADMC300 is a flexible, ...
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... PWM Operating Mode, MODECTRL and SYSSTAT Registers CLKOUT The PWM controller of the ADMC300 can operate in two distinct modes; single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 6 of the MODECTRL register. If this bit is cleared the PWM operates in the single update mode ...
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... DSP in double update mode. Width of the PWMSYNC Pulse, PWMSYNCWT Register The PWM controller of the ADMC300 produces an output PWM synchronization pulse at a rate equal to the PWM switch- ing frequency in single update mode and at twice the PWM frequency in the double update mode. This pulse is available for external use at the PWMSYNC pin ...
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... ADMC300 T PWMTM – PWMCHA – PWMDT = PWMTM S The minimum permissible T and sponding duty cycle similar fashion, the maximum value corresponding to a 100% duty cycle. S The output signals from the timing unit for operation in double update mode are shown in Figure 13. This illustrates a com- ...
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... The chopped active PWM signals may be required for the high- side drivers only, for the low-side drivers only or for both the high-side and low-side switches. Therefore, independent con- trol of this mode for both high- and low-side switches is included with two separate control bits in the PWMGATE register. ADMC300 2 PWMDT PWMTM ...
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... PWM will be disabled. The state of the PWMTRIP pin can be read from Bit 0 of the SYSSTAT register. The 12 PIO lines of the ADMC300 can also be configured to operate as PWM shutdown pins using the PIOPWM register. The 12-bit PIOPWM has a control bit for each PIO line (Bit 0 controls PIO0 etc ...
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... B input of the quadrature counter and the signal EIB becomes the A input of the quadrature counter. Therefore, if the EIA signal leads the EIB signal at the pins of the ADMC300, the A input to the quadrature counter will now lag the B input. This will be recognized as rotation in the reverse direction and the counter will be decremented on each quadrature pulse ...
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... ADMC300 Encoder Counter Reset The ZERO bit (Bit 1) of the EIUCTRL register determines if the encoder zero marker is used to reset the up/down counter of the encoder interface. When Bit 1 of the EIUCTRL register is set, the zero marker signal is used to reset the up/down counter to zero (if moving in the forward direction the value in the EIUMAXCNT register (if moving in the reverse direction) ...
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... READ Encoder Event Timer The Encoder Event Timer block forms an integral part of the EIU of the ADMC300. The EET accurately times the duration between encoder events. The information provided by the EET may be used to make allowances for the asynchronous timing of encoder and DSP-reading events result, more accurate computations of the position and velocity of the motor shaft may be performed ...
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... On reset, bits of the PIODIR register are cleared so that all 12 PIO pins are configured as inputs. In addition, all PIO lines are internally pulled down in the ADMC300 so that unconnected lines are seen as low level inputs. Three of the PIO lines also serve alternate functions. PIO9 is multiplexed as the external convert start signal for the ADC system ...
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... ETU0 and ETU1 inputs pins. Therefore, the ETU system can be used to compute the frequency, period, duty cycle or on-time of signals applied at the inputs. A functional block diagram of the ETU system of the ADMC300 is shown in Figure 18. ETU Event Definition The ETU system of the ADMC300 contains a dedicated 16-bit timer whose clock frequency may be programmed using the ETUDIVIDE register ...
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... IRQ2 interrupt enable bit (Bit 9) of the IMASK register and the appropriate bit of the PICMASK register must be set. The configuration of both the IMASK and PICMASK registers of the ADMC300 is shown at the end of the data sheet. Interrupt Vector Address 0x0004 (Highest Priority) ...
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... The ADMC300 uses SPORT1 as the default serial port for boot loading and as the interface to the development environment. There are two data receive pins, DR1A and DR1B, on the ADMC300. This permits DR1A to be used as the data receive pin when interfacing to serial ROM or E ing. Alternatively, if connecting through another external device for either boot loading or interface to the development environ- ment, the DR1B pin can be used ...
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... The monitor code in ROM automatically configures the SPORT1 pins during the boot sequence. Initially, the DR1SEL bit is cleared and the UARTEN bit is set so that the ADMC300 first attempts to perform a reset of the external memory device using the RFS1/SROM pin. This is accomplished by toggling the FL1 flag using the following code segment: SROMRESET: SET FL1 ...
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... PIOLEVEL 0x2041 PIOMODE 0x2042 PIOPWM 0x2043 0x2044 PIODIR 0x2045 PIODATA 0x2046 PIOINTEN 0x2047 PIOFLAG 0x2048–0x204F 0x2050 ETUA0 Table VIII. Peripheral Register Map of ADMC300 Bits [ [ [ [ [ [ [ [ [15 ...
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... ADMC300 Table VIII. Peripheral Register Map of ADMC300 (Continued) Address Name 0x2051 ETUB0 0x2052 ETUAA0 0x2053 ETUA1 0x2054 ETUB1 0x2055 ETUAA1 0x2056 ETUTIME 0x2057–0x205B 0x205C ETUCONFIG 0x205D ETUDIVIDE 0x205E ETUSTAT 0x205F ETUCTRL 0x2060 PWMSYNCWT 0x2061 PWMSWT 0x2062-0x20FF Address Name 0x3FFF SYSCNTL ...
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... ADCSYNC (R/ ADMC300 DM (0x2030 (0x2031) DM (0x2032) DM (0x2033) DM (0x2034 (0x2036) BANK A CONVERT START 0 = INTERNAL 1 = EXTERNAL BANK B CONVERT START BANK A MODE 0 = CONVST 1 = READ BANK B MODE MUX0 CONTROL ...
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... ADMC300 Default bit values are shown value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – these bits should always be written as shown. ...
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... PWMSYNCWT (R/ PWMSWT (R/ ADMC300 (0x2008) DM (0x200C) DM (0x200D) DM (0x200E (0x2009 (0x200A (0x200B GDCLK ...
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... ADMC300 RECEIVED FIRST ZERO MARKER 0 = NOT RECEIVED EIZP STATE EIB STATE EIA STATE ENABLE 0 = DISABLE 1 = EIUTIMER TIMEOUT 0 = EIUCNT READ 1 = ENABLE 0 = DISABLE Default bit values are shown value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – ...
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... EETDELTAT ( EETT ( EETSTAT( ADMC300 (0x2028 (0x2029 (0x202A (0x202B (0x202C OVERFLOW ENCODER EVENT TIMER OVERFLOW 1 = OVERFLOW ...
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... ADMC300 Default bit values are shown value is shown, the bit field is undefined at reset for R/W registers. Reserved bits are shown on a gray field – ...
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... ETUCTRL (R/ NOT CAPTURE ETU1 1 = START CAPTURE ADMC300 (0x2010) AUX0 DUTY CYCLE = AUXTIM0/256 (0x2011) AUX1 DUTY CYCLE = AUXTIM1/256 (0x2050) DM (0x2051) DM (0x2052) DM (0x2053) DM (0x2054) DM (0x2055) ...
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... ADMC300 PERIPHERAL (OR IRQ2) RESERVED (SET DISABLE (MASK) SPORT0 TRANSMIT 1 = ENABLE SPORT0 RECEIVE SOFTWARE PIO3 0 = DISABLE PIO2 (MASK ENABLE PIO1 PIO0 EVENT TIMER 0 = DISABLE 1 = ENABLE INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 ...
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... FI, FO, IRQ0, IRQ1, SCLK SPORT1 CONFIGURE 1 = SERIAL PORT MEMWAIT (R/ ADMC300 (0x2015 DR1B 0 = DR1A SPORT1 1 = UART MODE MODE 0 = SPORT MODE (0x2016) PWMTRIP PIN STATE WATCHDOG 1 = WATCHDOG TRIP FLAG ...
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... ADMC300 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead TQFP (ST-80) 0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.063 (1.60) MAX 0.549 (13.95) 0.486 (12.35) TYP 0.030 (0.75) 0.020 (0.50 SEATING PLANE TOP VIEW (PINS DOWN) 0.004 80 (0.10) 1 MAX 0.006 (0.15) 0.014 (0.35) 0.029 (0.73) 0.002 (0.05) 0.010 (0.25) 0.022 (0.57) 0.057 (1.45) 0.053 (1.35 ...