ADMC330BST Analog Devices, ADMC330BST Datasheet
ADMC330BST
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ADMC330BST Summary of contents
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... Word Data RAM 2K 24-Bit Word Program ROM REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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ADMC330–SPECIFICATIONS Parameter ANALOG-TO-DIGITAL CONVERTER Signal Input Resolution Converter Linearity Zero Offset Channel-to-Channel Comparator Match Comparator Delay Current Source Current Source Linearity ELECTRICAL CHARACTERISTICS V Logic Low IL V Logic High IH V Low-Level Output Voltage OL V Low-Level Output Voltage ...
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... Temperature Model Range ADMC330BST – +85 C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC330 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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ADMC330 Pin Pin Pin Pin Pin No. Type No. Type Name I/P VAUX3 O/P REFOUT 24 4 SUP GND GND 25 6 BIDIR PIO7 26 7 BIDIR PIO6 27 28 ...
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... The assembler has an algebraic syntax that is easy to program and debug. The linker combines object files into Visual DSP is a registered trademark of Analog Devices, Inc. REV executable file. The simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment ...
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ADMC330 four configuration registers (PWMTM, PWMDT, PWMPD and PWMGATE), which define basic waveform parameters such as the master switching frequency, deadtime, minimum pulsewidth, and gate drive chopping. There PWM output sig- nals on the pins AH through CL are controlled ...
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For example, the HCLK clock is 10 MHz kHz PWM waveforms are required, then PWMTM should be loaded with 10 MHz/8 kHz = 1250. A value must be written to the PWMTM register before the PWM block can ...
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ADMC330 Similar modifications can be made to Phases B and C using Bits 7 and 6, respectively, of the PWMSEG register. Six bits of the PWMSEG register (Bits are used to independently enable/disable any individual ...
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LOW SIDE GATE CHOPPING 1 = ENABLE 0 = DISABLE HIGH SIDE GATE CHOPPING CHANNEL CROSSOVER 1 = CROSSOVER B CHANNEL CROSSOVER CROSSOVER C CHANNEL CROSSOVER Figure 4. Configuration of PWMSEG and ...
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ADMC330 VIL t VIL T – T PWM CRST PWMSYNC COMPARATOR OUTPUT Figure 6. Analog Input Block Operation ADC Resolution Because the operation of the ADC is intrinsically linked to the PMW block, the effective resolution of ...
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PWMDAC 13k 10nF C1 C2 Figure 7. Auxiliary PWM Output Filter PROGRAMMABLE DIGITAL INPUT/OUTPUT The ADMC330 has eight programmable digital I/O (PIO) pins: PIO0–PIO7. Each pin can be individually configurable ...
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ADMC330 DATA DATA ADDRESS ADDRESS GENERATOR GENERATOR #2 #1 INPUT REGS INPUT REGS ALU MAC OUTPUT REGS OUTPUT REGS A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. The ...
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Serial Ports The ADMC330 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Following is a brief list of the capabilities of the ADMC330 SPORTs. Refer to the ADSP-2100 Family User’s Manual for further ...
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ADMC330 The interrupt control register, ICNTL, allows the external inter- rupts to be either edge- or level-sensitive. Since the IRQ2 line is a combination of all peripheral interrupt sources, they will all be set to edge- or level-sensitive. Level-sensitive is ...
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A software controlled full peripheral reset (including the watch- dog timer) is achieved by toggling the DSP FL2 flag from again. MEMORY MAP The ADMC330 has two types of memory: data memory and program memory. ...
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ADMC330 ICNTL IRQ0 SENSITIVITY IRQ1 SENSITIVITY IRQ2 SENSITIVITY INTERRUPT NESTING 1 = ENABLE DISABLE INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE 1 SOFTWARE 0 ...
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Address Offset (HEX) (Decimal) 0x2000 0 0x2001 1 0x2002 2 0x2003 3 0x2004 4 0x2005 5 0x2006 6 0x2007 7 0x2008 8 0x2009 9 0x200A 10 0x200B 11 0x200C 12 0x200D 13 0x200E 14 0x200F 15 0x2010 16 0x2011 17 ...
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ADMC330 Figure 13. Configuration of MODECTRL, SYSSTAT and IRQFLAG Registers MODECTRL (READ/WRITE ...
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TIMING PARAMETERS SERIAL PORTS Parameter Timing Requirement: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristic: t CLKOUT High to SCLK CC OUT t ...
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ADMC330 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead Plastic Thin Quad Flatpack (TQFP) (ST-80) 0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.063 (1.60) MAX 0.549 (13.95) 0.486 (12.35) TYP 0.030 (0.75) 0.020 (0.50 SEATING PLANE TOP VIEW ...