PALCE20V8H-25PC/4 Lattice Semiconductor, PALCE20V8H-25PC/4 Datasheet - Page 24

• Manufacturer Part Number: PALCE20V8H-25PC/4
• Description: EE CMOS 24-Pin Universal Programmable Array Logic
• Manufacturer: Lattice Semiconductor

POWER-UP RESET
The PALCE20V8 has been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH
independent of the logic polarity. This feature provides extra flexibility to the designer and is
especially valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide
range of ways V
power-up reset. These conditions are:
24
t
t
t
PR
S
WL
Parameter Symbol
The V
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Registered
CC
Power
Clock
Output
rise must be monotonic.
CC
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
can rise to its steady state, two conditions are required to ensure a valid
Parameter Descriptions
4 V
Figure 2. Power-Up Reset Waveform
PALCE20V8 Family
t
PR
t
WL
t
S
Min
See Switching Characteristics
Max
1000
V
CC
16491E-15
Unit
ns