PALCE20V8H-25PC/4 Lattice Semiconductor, PALCE20V8H-25PC/4 Datasheet - Page 4

• Manufacturer Part Number: PALCE20V8H-25PC/4
• Description: EE CMOS 24-Pin Universal Programmable Array Logic
• Manufacturer: Lattice Semiconductor

CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, the buffer is always
disabled. A macrocell configured as a dedicated input derives the input signal from an adjacent
I/O.
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0
through SL0
and SL1
through SL1
). SG0
0
7
0
7
determines whether registers will be allowed. SG1 determines whether the PALCE20V8 will
emulate a PAL20R8 family or a combinatorial device. Within each macrocell, SL0
, in conjunction
x
with SG1, selects the configuration of the macrocell and SL1
sets the output as either active low
x
or active high.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0
are the control signals for all four multiplexers. In MC
x
0
and MC
, SG0 replaces SG1 on the feedback multiplexer.
7
These configurations are summarized in Table 1 and illustrated in Figure 2.
If the PALCE20V8 is configured as a combinatorial device, the CLK and OE pins may be available
as inputs to the array. If the device is configured with registers, the CLK and OE pins cannot be
used as data inputs.
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
= 0. There is only one registered
x
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1
. SL1
is an input to the exclusive-OR gate which is the D input to the flip-
x
x
flop. SL1
is programmed as 1 for inverted output or 0 for non-inverted output. The flip-flop is
x
loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The
output buffer is enabled by OE.
Combinatorial Configurations
The PALCE20V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 0, and SL0
= 0. All eight product terms are available to
x
the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 18(21) and 19(23). Pins 18(21) and 19(23) do not use feedback in this mode.
Note:
1. The pin number without parentheses refers to the SKINNY DIP package. The pin number in parentheses refers to the PLCC
package.
4
PALCE20V8 Family