CY7C008 CYPRESS [Cypress Semiconductor], CY7C008 Datasheet - Page 10

• Manufacturer Part Number: CY7C008
• Description: 64K/128K x 8/9 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Document #: 38-06041 Rev. *C
Write Cycle No. 2: CE Controlled Timing
Write Cycle No. 1: R/W Controlled Timing
Notes:
27. R/W must be HIGH during all address transitions.
28. A write occurs during the overlap (t
29. t
30. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
31. To access RAM, CE = V
32. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
33. During this period, the I/O pins are in the output state, and input signals must not be applied.
34. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
CE
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
[28]
the bus for the required t
HA
[31]
R/W
R/W
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
OE
SD
IL
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
, SEM = V
(continued)
t
t
SA
SA
NOTE 33
IH
SCE
.
or t
PWE
) of a LOW CE or SEM.
t
[27, 28, 29, 34]
HZWE
[27, 28, 29, 30]
[32]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[30]
t
t
PWE
SD
SD
or (t
HZWE
+ t
SD
t
t
HA
HA
) to allow the I/O drivers to turn off and data to be placed on
t
t
HD
HD
t
LZWE
t
HZOE
CY7C008/009
CY7C018/019
[32]
NOTE 33
Page 10 of 19
PWE
.