CY7C008 CYPRESS [Cypress Semiconductor], CY7C008 Datasheet - Page 8

• Manufacturer Part Number: CY7C008
• Description: 64K/128K x 8/9 Dual-Port Static RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Data Retention Mode
The CY7C008/009 and CY7C018/019 are designed with bat-
tery backup in mind. Data retention voltage and supply current
are guaranteed over temperature. The following rules ensure
data retention:
Notes:
Document #: 38-06041 Rev. *C
19. Test conditions used are Load 1.
20. t
21. CE = V
1. Chip Enable (CE) must be held HIGH during data retention, with-
2. CE must be kept between V
3. The RAM can begin operation >t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
BLA
BHA
BLC
BHC
PS
WB
WH
BDD
INS
INR
SOP
SWRD
SPS
SAA
BUSY TIMING
INTERRUPT TIMING
SEMAPHORE TIMING
in V
during the power-up and power-down transitions.
imum operating voltage (4.5 volts).
Parameter
BDD
[20]
CC
is a calculated parameter and is the greater of t
CC
to V
, V
CC
in
= GND to V
– 0.2V.
[19]
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W HIGH after BUSY (Slave)
R/W HIGH after BUSY HIGH (Slave)
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
CC
[19]
, T
A
= 25°C. This parameter is guaranteed but not tested.
CC
Description
– 0.2V and 70% of V
Over the Operating Range
RC
after V
WDD
CC
–t
PWE
reaches the min-
(actual) or t
CC
DDD
[13]
–t
SD
(continued)
(actual).
Min.
10
11
5
0
5
5
Timing
V
CE
ICC
CC
-12
Parameter
DR1
[1]
Max.
12
12
12
12
12
12
12
12
CY7C008/009
CY7C018/019
Min.
13
10
5
0
5
5
4.5V
@ VCC
Data Retention Mode
Test Conditions
V
-15
CC
V
Max.
to V
CC
15
15
15
15
15
15
15
15
DR
> 2.0V
CC
= 2V
– 0.2V
Min.
15
10
5
0
5
5
[21]
4.5V
CY7C008/009
CY7C018/019
-20
Max.
Max.
20
20
20
17
20
20
20
20
1.5
V
Page 8 of 19
t
IH
RC
Unit
Unit
mA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns